On Wed, Sep 23, 2020 at 4:23 PM Radu Nicolau <radu.nico...@intel.com> wrote: > > Implement 2 new functions that will enable write combining > stores depending on architecture. The functions are provided > as a generic stub and a x86 specific implementation. > > The reason to implement these functions is to improve performance > by reducing the overhead associated with regular mmio writes when > updating the hardware queue tails and doorbells.
For the record, on which CPU/platform was this tested and how much of an improvement did you get with this? I did not see review/ack tokens from other arch maintainers, but since it has been on the ml for a while, I guess I can proceed as is. > > With this patch set the I40E, ICE, IXGBE and QAT PMDs are updated to > use the write combining store functions with other PMDs to follow. This series will go through the main repo: copying Ferruh and Akhil for info. -- David Marchand
