> -----Original Message----- > From: Pavan Nikhilesh Bhagavatula <pbhagavat...@marvell.com> > Sent: Sunday, September 13, 2020 9:11 PM > To: Van Haaren, Harry <harry.van.haa...@intel.com>; dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH] eal: add new prefetch0_write variant > > >This commit adds a new rte_prefetch0_write() variant, suggests to the > >compiler to use a prefetch instruction with intention to write. As a > >compiler builtin, the compiler can choose based on compilation target > >what the best implementation for this instruction is. > > Why not have the other variants too i.e. l2/l3/temporal store prefetches too?
Hi Pavan, Are there architectures that actually implement those? Usually for a WB mem store to complete, the data must be present in L1 cache (on x86 at least), and that's what the patch below with write0 achieves. I'm against adding all the variants "just in case", it leads to API bloat, and increases cognitive load on the programmer. My expectation is that in 99% of usage the prefetch write instruction should target L1. Cheers, -Harry > >Signed-off-by: Harry van Haaren <harry.van.haa...@intel.com> > > > >--- > > > >The integer constants passed to the builtin are not available as > >a #define value, and doing #defines just for this write variant > >does not seems a nice solution to me... particularly for those using > >IDEs where any #define value is auto-hinted for code-completion. > > > >--- > > lib/librte_eal/include/generic/rte_prefetch.h | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) <snip patch contents>
