> -----Original Message-----
> From: Ciara Power <ciara.po...@intel.com>
> Sent: Friday, August 7, 2020 11:59 PM
> To: dev@dpdk.org
> Cc: bruce.richard...@intel.com; Ciara Power <ciara.po...@intel.com>;
> Ruifeng Wang <ruifeng.w...@arm.com>; jer...@marvell.com; Honnappa
> Nagarahalli <honnappa.nagaraha...@arm.com>; David Christensen
> <d...@linux.vnet.ibm.com>
> Subject: [PATCH 20.11 02/12] eal: add default SIMD bitwidth values
>
> Each arch has a define for the default SIMD bitwidth value, this is used on
> EAL
> init to set the config max SIMD bitwidth.
>
> Cc: Ruifeng Wang <ruifeng.w...@arm.com>
> Cc: Jerin Jacob <jer...@marvell.com>
> Cc: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>
> Cc: David Christensen <d...@linux.vnet.ibm.com>
>
> Signed-off-by: Ciara Power <ciara.po...@intel.com>
> ---
> lib/librte_eal/arm/include/rte_vect.h | 2 ++
> lib/librte_eal/common/eal_common_options.c | 3 +++
> lib/librte_eal/include/generic/rte_vect.h | 2 ++
> lib/librte_eal/ppc/include/rte_vect.h | 2 ++
> lib/librte_eal/x86/include/rte_vect.h | 2 ++
> 5 files changed, 11 insertions(+)
>
> diff --git a/lib/librte_eal/arm/include/rte_vect.h
> b/lib/librte_eal/arm/include/rte_vect.h
> index 01c51712a1..7487a53862 100644
> --- a/lib/librte_eal/arm/include/rte_vect.h
> +++ b/lib/librte_eal/arm/include/rte_vect.h
> @@ -14,6 +14,8 @@
> extern "C" {
> #endif
>
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
I think for arm platform we should set it to '128'. It is the bit width of NEON
registers.
> +
> typedef int32x4_t xmm_t;
>
> #define XMM_SIZE (sizeof(xmm_t))
> diff --git a/lib/librte_eal/common/eal_common_options.c
> b/lib/librte_eal/common/eal_common_options.c
> index 90f4e8f5c3..c2a9624f89 100644
> --- a/lib/librte_eal/common/eal_common_options.c
> +++ b/lib/librte_eal/common/eal_common_options.c
> @@ -35,6 +35,7 @@
> #ifndef RTE_EXEC_ENV_WINDOWS
> #include <rte_telemetry.h>
> #endif
> +#include <rte_vect.h>
>
> #include "eal_internal_cfg.h"
> #include "eal_options.h"
> @@ -344,6 +345,8 @@ eal_reset_internal_config(struct internal_config
> *internal_cfg)
> internal_cfg->user_mbuf_pool_ops_name = NULL;
> CPU_ZERO(&internal_cfg->ctrl_cpuset);
> internal_cfg->init_complete = 0;
> + internal_cfg->max_simd_bitwidth.bitwidth =
> RTE_DEFAULT_SIMD_BITWIDTH;
> + internal_cfg->max_simd_bitwidth.locked = 0;
> }
>
> static int
> diff --git a/lib/librte_eal/include/generic/rte_vect.h
> b/lib/librte_eal/include/generic/rte_vect.h
> index 3fc47979f8..e98f184a97 100644
> --- a/lib/librte_eal/include/generic/rte_vect.h
> +++ b/lib/librte_eal/include/generic/rte_vect.h
> @@ -14,6 +14,8 @@
>
> #include <stdint.h>
>
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
> +
> /* Unsigned vector types */
>
> /**
> diff --git a/lib/librte_eal/ppc/include/rte_vect.h
> b/lib/librte_eal/ppc/include/rte_vect.h
> index b0545c878c..70fbd0c423 100644
> --- a/lib/librte_eal/ppc/include/rte_vect.h
> +++ b/lib/librte_eal/ppc/include/rte_vect.h
> @@ -15,6 +15,8 @@
> extern "C" {
> #endif
>
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
> +
> typedef vector signed int xmm_t;
>
> #define XMM_SIZE (sizeof(xmm_t))
> diff --git a/lib/librte_eal/x86/include/rte_vect.h
> b/lib/librte_eal/x86/include/rte_vect.h
> index df5a607623..b1df75aca7 100644
> --- a/lib/librte_eal/x86/include/rte_vect.h
> +++ b/lib/librte_eal/x86/include/rte_vect.h
> @@ -35,6 +35,8 @@
> extern "C" {
> #endif
>
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
> +
> typedef __m128i xmm_t;
>
> #define XMM_SIZE (sizeof(xmm_t))
> --
> 2.17.1
