For naw the rte_atomic128_cmp_exchange() is available on x86-64
and ARM64 architectures. The patch fixes the compilation condition
for the code using this atomic transaction.
Fixes: 244788055199 ("net/mlx5: introduce clock queue service routine")
Signed-off-by: Viacheslav Ovsiienko <viachesl...@mellanox.com>
---
drivers/net/mlx5/mlx5_txpp.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c
index 42776b8..cdb0079 100644
--- a/drivers/net/mlx5/mlx5_txpp.c
+++ b/drivers/net/mlx5/mlx5_txpp.c
@@ -644,7 +644,15 @@
* update by hardware with soecified rate. We have to
* read timestump and WQE completion index atomically.
*/
-#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_32)
+#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64)
+ rte_int128_t src;
+
+ memset(&src, 0, sizeof(src));
+ *ts = src;
+ /* if (*from == *ts) *from = *src else *ts = *from; */
+ rte_atomic128_cmp_exchange(from, ts, &src, 0,
+ __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+#else
rte_atomic64_t *cqe = (rte_atomic64_t *)from;
/* Power architecture does not support 16B compare-and-swap. */
@@ -665,14 +673,6 @@
ps[1] = op;
return;
}
-#else
- rte_int128_t src;
-
- memset(&src, 0, sizeof(src));
- *ts = src;
- /* if (*from == *ts) *from = *src else *ts = *from; */
- rte_atomic128_cmp_exchange(from, ts, &src, 0,
- __ATOMIC_RELAXED, __ATOMIC_RELAXED);
#endif
}
--
1.8.3.1
