> -----Original Message-----
> From: Phil Yang <phil.y...@arm.com>
> Sent: Thursday, July 2, 2020 12:27 AM
> To: Carrillo, Erik G <erik.g.carri...@intel.com>; dev@dpdk.org
> Cc: jer...@marvell.com; honnappa.nagaraha...@arm.com;
> d...@linux.vnet.ibm.com; ruifeng.w...@arm.com;
> dharmik.thak...@arm.com; n...@arm.com
> Subject: [PATCH v2 4/4] eventdev: relax smp barriers with c11 atomics
>
> The implementation-specific opaque data is shared between arm and cancel
> operations. The state flag acts as a guard variable to make sure the update of
> opaque data is synchronized. This patch uses c11 atomics with explicit one
> way memory barrier instead of full barriers rte_smp_w/rmb() to synchronize
> the opaque data between timer arm and cancel threads.
>
> Signed-off-by: Phil Yang <phil.y...@arm.com>
> Reviewed-by: Dharmik Thakkar <dharmik.thak...@arm.com>
> Reviewed-by: Ruifeng Wang <ruifeng.w...@arm.com>
Acked-by: Erik Gabriel Carrillo <erik.g.carri...@intel.com>
