New cn98xx SOC comes up with two NIX blocks wrt
cn96xx, cn93xx, to achieve higher performance.
Adding support for cn98xx where need a logic to
detect if the LF is attached to NIX0 or NIX1 and
then accordingly use the respective NIX block.
Signed-off-by: Harman Kalra <hka...@marvell.com>
---
doc/guides/platform/octeontx2.rst | 1 +
drivers/common/octeontx2/hw/otx2_rvu.h | 3 ++-
drivers/net/octeontx2/otx2_ethdev.c | 17 ++++++++++++++++-
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/doc/guides/platform/octeontx2.rst
b/doc/guides/platform/octeontx2.rst
index 15b1641cf..13255eec5 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -13,6 +13,7 @@ More information about OCTEON TX2 SoC can be found at
`Marvell Official Website
Supported OCTEON TX2 SoCs
-------------------------
+- CN98xx
- CN96xx
- CN93xx
diff --git a/drivers/common/octeontx2/hw/otx2_rvu.h
b/drivers/common/octeontx2/hw/otx2_rvu.h
index f2037ec57..330bfb37f 100644
--- a/drivers/common/octeontx2/hw/otx2_rvu.h
+++ b/drivers/common/octeontx2/hw/otx2_rvu.h
@@ -134,11 +134,12 @@
#define RVU_BLOCK_ADDR_RVUM (0x0ull)
#define RVU_BLOCK_ADDR_LMT (0x1ull)
#define RVU_BLOCK_ADDR_NPA (0x3ull)
+#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
+#define RVU_BLOCK_ADDR_NIX1 (0x5ull)
#define RVU_BLOCK_ADDR_NPC (0x6ull)
#define RVU_BLOCK_ADDR_SSO (0x7ull)
#define RVU_BLOCK_ADDR_SSOW (0x8ull)
#define RVU_BLOCK_ADDR_TIM (0x9ull)
-#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
#define RVU_BLOCK_ADDR_CPT0 (0xaull)
#define RVU_BLOCK_ADDR_NDC0 (0xcull)
#define RVU_BLOCK_ADDR_NDC1 (0xdull)
diff --git a/drivers/net/octeontx2/otx2_ethdev.c
b/drivers/net/octeontx2/otx2_ethdev.c
index 3f3f0a693..095506034 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -2177,6 +2177,20 @@ otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
return false;
}
+static inline uint64_t
+nix_get_blkaddr(struct otx2_eth_dev *dev)
+{
+ uint64_t reg;
+
+ /* Reading the discovery register to know which NIX is the LF
+ * attached to.
+ */
+ reg = otx2_read64(dev->bar2 +
+ RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
+
+ return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
+}
+
static int
otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
{
@@ -2236,7 +2250,6 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
dev->configured = 0;
dev->drv_inited = true;
dev->ptype_disable = 0;
- dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
/* Attach NIX LF */
@@ -2244,6 +2257,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
if (rc)
goto otx2_npa_uninit;
+ dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);
+
/* Get NIX MSIX offset */
rc = nix_lf_get_msix_offset(dev);
if (rc)
--
2.18.0
