26/04/2020 16:45, Phil Yang: > Volatile has no ordering semantics. The rte_timer structure defines > timer status as a volatile variable and uses the rte_r/wmb barrier > to guarantee inter-thread visibility. > > This patch optimized the volatile operation with c11 atomic operations > and one-way barrier to save the performance penalty. According to the > timer_perf_autotest benchmarking results, this patch can uplift 10%~16% > timer appending performance, 3%~20% timer resetting performance and 45% > timer callbacks scheduling performance on aarch64 and no loss in > performance for x86. > > Suggested-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com> > Signed-off-by: Phil Yang <phil.y...@arm.com> > Reviewed-by: Gavin Hu <gavin...@arm.com> > Acked-by: Erik Gabriel Carrillo <erik.g.carri...@intel.com>
Applied, thanks
