> -----Original Message----- > From: Carrillo, Erik G <erik.g.carri...@intel.com> > Sent: Sunday, April 26, 2020 8:19 PM > To: Phil Yang <phil.y...@arm.com>; tho...@monjalon.net > Cc: rsanf...@akamai.com; dev@dpdk.org; david.march...@redhat.com; > Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>; Gavin Hu > <gavin...@arm.com>; nd <n...@arm.com>; nd <n...@arm.com> > Subject: RE: [dpdk-dev] [PATCH v3] lib/timer: relax barrier for status update > > > > > -----Original Message----- > > From: Phil Yang <phil.y...@arm.com> > > Sent: Sunday, April 26, 2020 2:36 AM > > To: tho...@monjalon.net > > Cc: Carrillo, Erik G <erik.g.carri...@intel.com>; rsanf...@akamai.com; > > dev@dpdk.org; david.march...@redhat.com; Honnappa Nagarahalli > > <honnappa.nagaraha...@arm.com>; Gavin Hu <gavin...@arm.com>; nd > > <n...@arm.com>; nd <n...@arm.com> > > Subject: RE: [dpdk-dev] [PATCH v3] lib/timer: relax barrier for status > update > > > > > -----Original Message----- > > > From: Thomas Monjalon <tho...@monjalon.net> > > > Sent: Sunday, April 26, 2020 1:18 AM > > > To: Phil Yang <phil.y...@arm.com> > > > Cc: erik.g.carri...@intel.com; rsanf...@akamai.com; dev@dpdk.org; > > > david.march...@redhat.com; Honnappa Nagarahalli > > > <honnappa.nagaraha...@arm.com>; Gavin Hu <gavin...@arm.com>; nd > > > <n...@arm.com> > > > Subject: Re: [dpdk-dev] [PATCH v3] lib/timer: relax barrier for status > > > update > > > > > > 24/04/2020 09:24, Phil Yang: > > > > Volatile has no ordering semantics. The rte_timer structure defines > > > > timer status as a volatile variable and uses the rte_r/wmb barrier > > > > to guarantee inter-thread visibility. > > > > > > > > This patch optimized the volatile operation with c11 atomic > > > > operations and one-way barrier to save the performance penalty. > > > > According to the timer_perf_autotest benchmarking results, this > > > > patch can uplift 10%~16% timer appending performance, 3%~20% timer > > > > resetting performance and > > > 45% > > > > timer callbacks scheduling performance on aarch64 and no loss in > > > > performance for x86. > > > > > > > > Suggested-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com> > > > > Signed-off-by: Phil Yang <phil.y...@arm.com> > > > > Reviewed-by: Gavin Hu <gavin...@arm.com> > > > > Acked-by: Erik Gabriel Carrillo <erik.g.carri...@intel.com> > > > [...] > > > > --- a/lib/librte_timer/rte_timer.h > > > > +++ b/lib/librte_timer/rte_timer.h > > > > @@ -101,7 +101,7 @@ struct rte_timer > > > > - volatile union rte_timer_status status; /**< Status of timer. */ > > > > + union rte_timer_status status; /**< Status of timer. */ > > > > > > Unfortunately, I cannot merge this patch because it breaks the ABI: > > > > > > [C]'function void rte_timer_init(rte_timer*)' at rte_timer.c:214:1 > > > has some indirect sub-type changes: > > > parameter 1 of type 'rte_timer*' has sub-type changes: > > > in pointed to type 'struct rte_timer' at rte_timer.h:100:1: > > > type size hasn't changed > > > 1 data member changes (2 filtered): > > > type of 'volatile rte_timer_status rte_timer::status' changed: > > > entity changed from 'volatile rte_timer_status' to 'union > > > rte_timer_status' at rte_timer.h:67:1 > > > type size hasn't changed > > > > > > > I think we can revert it to the original definition of rte_timer and keep > > the > > union rte_timer_status volatile-qualified. > > Because with or without this 'volatile' qualify, it generates the same code > on > > aarch64 and x86. > > So it seems acceptable to ignore it to make the ABI compatible? > > > > Thank, > > Phil > > I was wondering about this also. Is the performance improvement on > aarch64 still the same in that case?
Yes. it is. It got the same performance improvement on aarch64 and no performance loss on x86. I will update it in v4.
