On Fri, Jan 31, 2020 at 6:21 PM <pbhagavat...@marvell.com> wrote:
>
> From: Pavan Nikhilesh <pbhagavat...@marvell.com>
>
> OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate
> the set selection.
> Add additional padding to ensure that the element size always
> occupies odd number of cachelines to ensure even distribution
> of elements among L1D cache sets.
>
> Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com>
> Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
> Signed-off-by: Vamsi Attunuru <vattun...@marvell.com>
> Signed-off-by: Jerin Jacob <jer...@marvell.com>
> ---
> drivers/mempool/octeontx2/otx2_mempool_ops.c | 41 ++++++++++++++++++++
> 1 file changed, 41 insertions(+)
Please fix the 32-bit build issues(i.e use PRIx64)
/export/dpdk.org/drivers/mempool/octeontx2/otx2_mempool_ops.c:782:41:
note: format string is defined here
782 | otx2_npa_dbg("iova %lx, aligned iova %lx", iova - off, iova);
| ~~^
| |
| long unsigned int
| %llx
