Hi,
> -----Original Message-----
> From: Viacheslav Ovsiienko <viachesl...@mellanox.com>
> Sent: Friday, November 15, 2019 1:35 PM
> To: dev@dpdk.org
> Cc: Matan Azrad <ma...@mellanox.com>; Raslan Darawsheh
> <rasl...@mellanox.com>; Ori Kam <or...@mellanox.com>
> Subject: [PATCH] net/mlx5: fix Tx doorbell write memory barrier
>
> As the result of testing it was found that some hosts have
> the performance penalty imposed by required write memory barrier
> after doorbell writing. Before 19.08 release there was some
> heuristics to decide whether write memory barrier should be
> performed. For the bursts of recommended size (or multiple)
> it was supposed there were some extra ongoing packets in the
> next burst and write memory barrier may be skipped (supposed
> to be performed in the next burst, at least after descriptor
> writing).
>
> This patch restores that behaviour, the devargs tx_db_nc=2
> must be specified to engage this performance tuning feature.
>
> Fixes: 8409a28573d3 ("net/mlx5: control transmit doorbell register mapping")
>
> Signed-off-by: Viacheslav Ovsiienko <viachesl...@mellanox.com>
> ---
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
