On Tue, Sep 3, 2019 at 1:00 PM <jer...@marvell.com> wrote:
>
> From: Jerin Jacob <jer...@marvell.com>
>
> Implement XADD eBPF instruction using STADD arm64 instruction.
> If the given platform does not have atomics support,
> use LDXR and STXR pair for critical section instead of STADD.
For the record, this patch had a missed dependency on the 128-bits
atomic for arm64 patch because of RTE_ARM_FEATURE_ATOMICS.
This will be resolved once the latter is merged.
> ---
> lib/librte_bpf/bpf_jit_arm64.c | 85 +++++++++++++++++++++++++++++++++-
> 1 file changed, 84 insertions(+), 1 deletion(-)
>
> diff --git a/lib/librte_bpf/bpf_jit_arm64.c b/lib/librte_bpf/bpf_jit_arm64.c
> index c797c9c62..62fa6a505 100644
> --- a/lib/librte_bpf/bpf_jit_arm64.c
> +++ b/lib/librte_bpf/bpf_jit_arm64.c
[snip]
> +static int
> +has_atomics(void)
> +{
> + int rc = 0;
> +
> +#if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
> + rc = 1;
> +#endif
> + return rc;
> +}
[snip]
--
David Marchand
