This patch reserves several bits as input set selection from the
high end of the 64 bits. It is combined with exisiting ETH_RSS_*
to represent RSS types. This patch also checks the simultaneous
use of SRC_ONLY and DST_ONLY of the same level.
Signed-off-by: Simei Su <simei...@intel.com>
Reviewed-by: Qi Zhang <qi.z.zh...@intel.com>
Acked-by: Ori Kam <or...@mellanox.com>
---
lib/librte_ethdev/rte_ethdev.c | 5 +++++
lib/librte_ethdev/rte_ethdev.h | 25 +++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c
index 7caaa0b..69a3d71 100644
--- a/lib/librte_ethdev/rte_ethdev.c
+++ b/lib/librte_ethdev/rte_ethdev.c
@@ -1269,6 +1269,9 @@ struct rte_eth_dev *
goto rollback;
}
+ RTE_ETH_RSS_HF_REFINE(dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf,
+ dev_conf->rx_adv_conf.rss_conf.rss_hf);
+
/* Check that device supports requested rss hash functions. */
if ((dev_info.flow_type_rss_offloads |
dev_conf->rx_adv_conf.rss_conf.rss_hf) !=
@@ -3112,6 +3115,8 @@ struct rte_eth_dev *
if (ret != 0)
return ret;
+ RTE_ETH_RSS_HF_REFINE(rss_conf->rss_hf, rss_conf->rss_hf);
+
dev = &rte_eth_devices[port_id];
if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) !=
dev_info.flow_type_rss_offloads) {
diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h
index 40aa6a3..389a3e6 100644
--- a/lib/librte_ethdev/rte_ethdev.h
+++ b/lib/librte_ethdev/rte_ethdev.h
@@ -165,6 +165,17 @@
#define RTE_ETHDEV_LOG(level, ...) \
rte_log(RTE_LOG_ ## level, rte_eth_dev_logtype, "" __VA_ARGS__)
+#define RTE_ETH_RSS_HF_REFINE(output, input) do { \
+ if ((input & ETH_RSS_L3_SRC_ONLY) && \
+ (input & ETH_RSS_L3_DST_ONLY)) \
+ output = input & (~(ETH_RSS_L3_SRC_ONLY | \
+ ETH_RSS_L3_DST_ONLY)); \
+ if ((input & ETH_RSS_L4_SRC_ONLY) && \
+ (input & ETH_RSS_L4_DST_ONLY)) \
+ output = input & (~(ETH_RSS_L4_SRC_ONLY | \
+ ETH_RSS_L4_DST_ONLY)); \
+} while (0)
+
struct rte_mbuf;
/**
@@ -507,6 +518,20 @@ struct rte_eth_rss_conf {
#define ETH_RSS_NVGRE (1ULL << 21)
#define ETH_RSS_GTPU (1ULL << 23)
+/*
+ * We use the following macros to combine with above ETH_RSS_* for
+ * more specific input set selection. These bits are defined starting
+ * from the high end of the 64 bits.
+ * Note: If we use above ETH_RSS_* without SRC/DST_ONLY, it represents
+ * both SRC and DST are taken into account. If SRC_ONLY and DST_ONLY of
+ * the same level are used simultaneously, it is the same case as none of
+ * them are added.
+ */
+#define ETH_RSS_L3_SRC_ONLY (1ULL << 63)
+#define ETH_RSS_L3_DST_ONLY (1ULL << 62)
+#define ETH_RSS_L4_SRC_ONLY (1ULL << 61)
+#define ETH_RSS_L4_DST_ONLY (1ULL << 60)
+
#define ETH_RSS_IP ( \
ETH_RSS_IPV4 | \
ETH_RSS_FRAG_IPV4 | \
--
1.8.3.1
