All, We finish the basic and performance test using this backported version on CVL 100 B0. The test result is the same as 19.08’s.
SW configuration: DPDK version:18.11.2 Firmware version: 0.50 0x80001658 1.2186.0 Driver version: 0.11.2_rc9 PKG: ice-1.2.5.0.secure.pkg Basic test lists： uni_pkt: failed in l2pkt_detect and nsh mac_filter: Passed pmdrssreta: Passed tx_preparation: Passed jumboframes: Passed shutdown_api: Passed TestSuite_hello_world: Passed Blacklist: Passed Tso: Passed Coremask: Passed. Vlan: Passed Ipgre: Failed in GRE_ipv6_packet_detect. Know issue of DPDK bug 15071. dual_vlan: failed in vlan_synthetic_test, vlan_tpid_config，vlan_stripq_config and vlan_random_test checksum_offload: Passed vlan_ethertype_config: Failed. Known issue of DPDK bug 15072. pmdpcap: Passed link_status_interrupt: Failed. Known issue of DPDK bug 14025 TestSuite_userspace_ethtool: failed. Known issue of DPDK bug 2513. Perpormance test: test data/throughput is the same as 19.08. - single core test - zero packet loss test Regards, Yu Ping From: Kolodziej, KacperX Sent: Tuesday, September 17, 2019 8:02 PM To: Mcnamara, John <john.mcnam...@intel.com>; Chen, Zhaoyan <zhaoyan.c...@intel.com> Cc: Modrak, PawelX <pawelx.mod...@intel.com>; Yu, Liting <liting...@intel.com>; Xu, Qian Q <qian.q...@intel.com>; Richardson, Bruce <bruce.richard...@intel.com>; Zapolski, MarcinX A <marcinx.a.zapol...@intel.com>; Baran, MarcinX <marcinx.ba...@intel.com>; Yu, PingX <pingx...@intel.com>; Stokes, Ian <ian.sto...@intel.com>; Peng, Yuan <yuan.p...@intel.com>; Walsh, Richard <richard.wa...@intel.com> Subject: RE: PoC for Backporting Hello, We have tested backported version only on CVL_B0_100G_2PORTS. We have probably used ice-0.11.2_rc9. Regards, Kacper Kołodziej --------------------------------------------------------------------- Intel Corporation (UK) Limited Registered No. 1134945 (England) Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47 From: Mcnamara, John Sent: Tuesday, September 17, 2019 1:52 PM To: Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> Cc: Modrak, PawelX <pawelx.mod...@intel.com<mailto:pawelx.mod...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Zapolski, MarcinX A <marcinx.a.zapol...@intel.com<mailto:marcinx.a.zapol...@intel.com>>; Baran, MarcinX <marcinx.ba...@intel.com<mailto:marcinx.ba...@intel.com>>; Kolodziej, KacperX <kacperx.kolodz...@intel.com<mailto:kacperx.kolodz...@intel.com>>; Yu, PingX <pingx...@intel.com<mailto:pingx...@intel.com>>; Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Walsh, Richard <richard.wa...@intel.com<mailto:richard.wa...@intel.com>> Subject: Re: PoC for Backporting + Richard, who is also using a CVL back port as part of an application. John On 17 Sep 2019, at 07:51, Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> wrote: + Ping, our CW PM into our loop. Regards, Zhaoyan Chen From: Modrak, PawelX Sent: Tuesday, September 17, 2019 2:10 PM To: Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Zapolski, MarcinX A <marcinx.a.zapol...@intel.com<mailto:marcinx.a.zapol...@intel.com>>; Baran, MarcinX <marcinx.ba...@intel.com<mailto:marcinx.ba...@intel.com>>; Kolodziej, KacperX <kacperx.kolodz...@intel.com<mailto:kacperx.kolodz...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>> Subject: RE: PoC for Backporting Hi Kacper, Can you look at below table and check if this is setup we used for backport testing? Best regards, Pawel From: Chen, Zhaoyan Sent: Tuesday, September 17, 2019 8:04 AM To: Modrak, PawelX <pawelx.mod...@intel.com<mailto:pawelx.mod...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Zapolski, MarcinX A <marcinx.a.zapol...@intel.com<mailto:marcinx.a.zapol...@intel.com>>; Baran, MarcinX <marcinx.ba...@intel.com<mailto:marcinx.ba...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> Subject: RE: PoC for Backporting Thanks, Pawel, Just confirm the test environment, my understand, since we backport 19.08 -> 18.11 LTS for CVL support and CLX support. So our testing is focus on · CLX platform · CVL NIC PMD with following firmware version/driver version/package version · and private repo ssh://g...@gitlab.devtools.intel.com:29418/CoreDataPlane/dpdk-stable.git on pawel_back-porting_19.08_cvl_pmd branch CVL_A1_100G_2PORTS(Apha4) 0.40 0x80000fb0 1.2.0.2 0.10.1 (ice) We 0.50 0x80001658 1.2.5.0 0.11.2_rc9 (ice) CVL_B0_25G_4PORTS 0.50 0x80001657 1.2.5.0 0.11.2_rc9 (ice) Please confirm, if any question, please let me know. Regards, Zhaoyan Chen From: Modrak, PawelX Sent: Thursday, September 12, 2019 8:24 PM To: Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Zapolski, MarcinX A <marcinx.a.zapol...@intel.com<mailto:marcinx.a.zapol...@intel.com>>; Baran, MarcinX <marcinx.ba...@intel.com<mailto:marcinx.ba...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> Subject: RE: PoC for Backporting Hi John, I added comment to DPDK-11027: I pushed ported ice to ssh://g...@gitlab.devtools.intel.com:29418/CoreDataPlane/dpdk-stable.git on pawel_back-porting_19.08_cvl_pmd branch. Below is a list of changes I made to original ice implementation: 1. General: * delete rte_ and RTE_ prefix for some structs and defines (I used sed) 1. ice_ethdev.c: * removed lines 2113 and 2114 because there is no max_mtu and min_mtu in rte_eth_dev_info struct: * dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD; dev_info->min_mtu = ETHER_MIN_MTU; * replace rte_intr_ack with rte_intr_enable to use old method for acking an interrupt in interrupt handlers. 1. ice_switch_filter.h: * add include: * #include <rte_flow.h> I used dpdk-stable-intel/18.11 branch (latest commit was 6fc5c48f0), you can check on pawel_back-porting_19.08_cvl_pmd branch. Best regards, Pawel From: Mcnamara, John Sent: Thursday, September 12, 2019 9:21 AM To: Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Zapolski, MarcinX A <marcinx.a.zapol...@intel.com<mailto:marcinx.a.zapol...@intel.com>>; Baran, MarcinX <marcinx.ba...@intel.com<mailto:marcinx.ba...@intel.com>>; Modrak, PawelX <pawelx.mod...@intel.com<mailto:pawelx.mod...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> Subject: RE: PoC for Backporting + Mobica devs. Guys, can one of you send the link to the CVL backport repo and add any instructions required to apply the patches: for example the version that the patches should be applied against. Thanks, John From: Yu, Liting Sent: Thursday, September 12, 2019 6:53 AM To: Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> Subject: RE: PoC for Backporting To follow up on this, can someone please advise who completed the development and can confirm the gitlab repo info? Thanks. From: Xu, Qian Q Sent: Monday, September 9, 2019 10:09 PM To: Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>> Subject: RE: PoC for Backporting Bruce I see, could you pls help give the gitlab repo info so that we can help check? Zhaoyan Could you ask CW to run the CVL basic regression when Bruce gives the git info? Thx. From: Richardson, Bruce Sent: Monday, September 9, 2019 5:56 PM To: Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> Subject: RE: PoC for Backporting This is CVL backporting under discussion here, so the NIC is CVL. The repo branch I don't know, but it will be a branch on our internal gitlab repos, I expect. From: Xu, Qian Q Sent: Monday, September 9, 2019 10:47 AM To: Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Peng, Yuan <yuan.p...@intel.com<mailto:yuan.p...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Chen, Zhaoyan <zhaoyan.c...@intel.com<mailto:zhaoyan.c...@intel.com>> Subject: RE: PoC for Backporting Bruce Could you give the clear test requirement? 1. Based on which commit, which repo? 2. Which NIC is needed here? FVL, CVL or NNT? From: Richardson, Bruce Sent: Monday, September 9, 2019 5:42 PM To: Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>> Subject: RE: PoC for Backporting Since this is not for upstreaming and just for verifying the work needed, functional testing alone should be ok, I believe. From: Xu, Qian Q Sent: Monday, September 9, 2019 10:36 AM To: Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>> Subject: RE: PoC for Backporting Liting/John/Bruce What kind of regression test needed? Functional test or performance test? On which NIC? From: Yu, Liting Sent: Friday, September 6, 2019 11:29 AM To: Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>>; Xu, Qian Q <qian.q...@intel.com<mailto:qian.q...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>> Subject: RE: PoC for Backporting Thanks for clarification John. Hi Qian, Re PoC for backporting, is it possible to request your team to do the validation test? The development task has been completed. We discussed this before. It looks like now that it’s more efficient to have your team perform the test instead of ramping up Mobica GBs. Kind regards, Liting From: Mcnamara, John Sent: Thursday, September 5, 2019 10:18 PM To: Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>> Subject: RE: PoC for Backporting Hi, > We had this discussion some time back. Ok. I missed that. I thought that this was only a development task. > At the time, you were trying to get the GBs to set up the hardware with > support from Qian’s team. Is this option now dropped? I may be wrong but I don't see this option as feasible. Setting up the DTF for validation is non-trivial. Even getting them a CVL system to test with, on the correct subnet, will be difficult. Someone correct me if I am wrong. Even if it is feasible it probably won't be efficient. > And I assume we will need to do the similar validation test again for the > real backporting after the POC. Are we looking to ramp up GBs then or still > need Qian’s team for validation? I don't know what was agreed previously but I think that testing by the STV team would be the best option. John From: Yu, Liting Sent: Thursday, September 5, 2019 11:03 AM To: Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>>; Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>> Subject: RE: PoC for Backporting Hi John, We had this discussion some time back. At the time, you were trying to get the GBs to set up the hardware with support from Qian’s team. Is this option now dropped? And I assume we will need to do the similar validation test again for the real backporting after the POC. Are we looking to ramp up GBs then or still need Qian’s team for validation? Thanks, Liting From: Mcnamara, John Sent: Thursday, September 5, 2019 5:45 PM To: Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>>; Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>> Cc: Stokes, Ian <ian.sto...@intel.com<mailto:ian.sto...@intel.com>> Subject: RE: PoC for Backporting Hi, The backport work is completed from a coding point of view. I wasn't aware, until Bruce pointed it out, that there is also a validation requirement to this task. I don't think that this is something that the Standard Interfaces GBs can do since the ramp on DTF and associated validation would take too long. We would also have issues with getting the right hardware for the task. So I'd suggest 2 options: 1. Ask Qian's STV team to do a one-off CVL validation of the backported driver. Liting can you raise this with Qian to see if this is possible. 2. Ask Ian's GB CVL validation GB to test it with OvS. This wouldn't be as rigorous/compelete as option 1. John From: Richardson, Bruce Sent: Thursday, September 5, 2019 9:27 AM To: Yu, Liting <liting...@intel.com<mailto:liting...@intel.com>> Cc: Mcnamara, John <john.mcnam...@intel.com<mailto:john.mcnam...@intel.com>> Subject: RE: PoC for Backporting No, sorry, not yet. Adding John on the off-chance he has any visibility of it. From: Yu, Liting Sent: Thursday, September 5, 2019 6:13 AM To: Richardson, Bruce <bruce.richard...@intel.com<mailto:bruce.richard...@intel.com>> Subject: PoC for Backporting Hi Bruce, Did you find out the latest status of PoC for backporting? Thanks, Liting
