Hi,
> -----Original Message-----
> From: dev <dev-boun...@dpdk.org> On Behalf Of Dekel Peled
> Sent: Thursday, August 1, 2019 4:23 PM
> To: Yongseok Koh <ys...@mellanox.com>; Slava Ovsiienko
> <viachesl...@mellanox.com>; Shahaf Shuler <shah...@mellanox.com>
> Cc: Ori Kam <or...@mellanox.com>; dev@dpdk.org
> Subject: [dpdk-dev] [PATCH v2] net/mlx5: fix limit on direct rules tables
> number
>
> MLX5 PMD limits the number of SW steering tables to 32.
> This patch updates the limit to 65535, to allow wide range of values.
>
> Fixes: e2b4925ef7c1 ("net/mlx5: support Direct Rules E-Switch")
>
> v2: remove Cc to stable release, not relevant for this fix.
>
> Signed-off-by: Dekel Peled <dek...@mellanox.com>
> ---
> drivers/net/mlx5/mlx5.h | 4 ++--
> drivers/net/mlx5/mlx5_flow_dv.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
> index caf2491..f559f83 100644
> --- a/drivers/net/mlx5/mlx5.h
> +++ b/drivers/net/mlx5/mlx5.h
> @@ -513,8 +513,8 @@ struct mlx5_flow_tbl_resource {
> rte_atomic32_t refcnt; /**< Reference counter. */
> };
>
> -#define MLX5_MAX_TABLES 1024
> -#define MLX5_MAX_TABLES_FDB 32
> +#define MLX5_MAX_TABLES 0xffff
> +#define MLX5_MAX_TABLES_FDB 0xffff
> #define MLX5_GROUP_FACTOR 1
>
> #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c
> index 9c0a261..14e70ed 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -2817,7 +2817,7 @@ struct field_modify_info modify_tcp[] = {
> (error, EINVAL,
> RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
> NULL, "group must be smaller than "
> - RTE_STR(MLX5_MAX_FDB_TABLES));
> + RTE_STR(MLX5_MAX_TABLES_FDB));
> }
> if (!(attributes->egress ^ attributes->ingress))
> return rte_flow_error_set(error, ENOTSUP,
> --
> 1.8.3.1
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
