> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Aaron Conole
> Sent: Thursday, July 25, 2019 2:28 PM
> hgovindh <hariprasad.govindhara...@intel.com> writes:
>
> > Fix unaligned memory access when reading IPv6 header which leads to
> > segmentation fault by changing aligned memory read to unaligned memory
> > read.
> >
> > Bugzilla ID: 279
> > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > Cc: maciej.cze...@caviumnetworks.com
> > Cc: sta...@dpdk.org
> > Signed-off-by: hgovindh <hariprasad.govindhara...@intel.com>
> > ---
> > examples/l3fwd/l3fwd_em.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> > index fa8f82be6..f0c443dae 100644
> > --- a/examples/l3fwd/l3fwd_em.c
> > +++ b/examples/l3fwd/l3fwd_em.c
> > @@ -285,7 +285,7 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t
> portid, void *lookup_struct)
> > * Get part of 5 tuple: dst IP address lower 96 bits
> > * and src IP address higher 32 bits.
> > */
> > - key.xmm[1] = *(xmm_t *)data1;
> > + key.xmm[1] = _mm_loadu_si128((xmm_t *)data1);
>
> Nak. Please use a generic unaligned load, rather than an intel specific one.
> Otherwise, supported platforms like arm64 will have broken builds.
>
> Additionally, which chip and compiler did you use to get this error?
This comes from Bugzilla, the compiler used there is GCC 8.2.0 and the CPU is
Intel Core i5,
As far as I know this can also be reproduced on Intel Xeon, with GCC 8.3.0,
in both cases its compiled with compiler optimizations disabled.
>
> >
> > /*
> > * Get part of 5 tuple: dst port and src port
