> -----Original Message-----
> From: Nithin Dabilpuram <ndabilpu...@marvell.com>
> Sent: Wednesday, July 10, 2019 10:32 PM
> To: Jerin Jacob Kollanukkaran <jer...@marvell.com>; Nithin Kumar
> Dabilpuram <ndabilpu...@marvell.com>; Vamsi Krishna Attunuru
> <vattun...@marvell.com>; John McNamara <john.mcnam...@intel.com>;
> Marko Kovacevic <marko.kovace...@intel.com>; Pavan Nikhilesh
> Bhagavatula <pbhagavat...@marvell.com>; Kiran Kumar Kokkilagadda
> <kirankum...@marvell.com>
> Cc: dev@dpdk.org
> Subject: [PATCH] common/octeontx2: add CNF95xx SoC support
>
> Update platform support of CNF95xx in documentation and also, update the
> HW cap based on PCI subsystem id and revision id.
> This patch also changes HW capability handling to be based on PCI Revision
> ID. PCI Revision ID contains a unique identifier to identify chip, major and
> minor revisions.
>
> Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
> pci_dev = container_of(event_dev->dev, struct rte_pci_device,
> device);
> + rc = rte_pci_read_config(pci_dev, &rev_id, 1,
> RVU_PCI_REVISION_ID);
> + if (rc != 1) {
> + otx2_err("Failed to read pci revision id, rc=%d", rc);
> + goto error;
> + }
Please remove this code duplication in all the drivers.
Other that it looks good to me.
