From: Jerin Jacob <jer...@marvell.com>
add various devargs command line options supported by
this driver.
Signed-off-by: Jerin Jacob <jer...@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpu...@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavat...@marvell.com>
Signed-off-by: Kiran Kumar K <kirankum...@marvell.com>
---
drivers/net/octeontx2/Makefile | 3 +-
drivers/net/octeontx2/meson.build | 1 +
drivers/net/octeontx2/otx2_ethdev.c | 7 +
drivers/net/octeontx2/otx2_ethdev.h | 20 +++
drivers/net/octeontx2/otx2_ethdev_devargs.c | 143 ++++++++++++++++++++
drivers/net/octeontx2/otx2_rx.h | 10 ++
6 files changed, 183 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/octeontx2/otx2_ethdev_devargs.c
create mode 100644 drivers/net/octeontx2/otx2_rx.h
diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile
index 9ca1eea99..dbcfec5b4 100644
--- a/drivers/net/octeontx2/Makefile
+++ b/drivers/net/octeontx2/Makefile
@@ -31,7 +31,8 @@ LIBABIVER := 1
#
SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \
otx2_mac.c \
- otx2_ethdev.c
+ otx2_ethdev.c \
+ otx2_ethdev_devargs.c
LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_common_octeontx2 -lm
LDLIBS += -lrte_ethdev -lrte_net -lrte_kvargs -lrte_bus_pci
-lrte_mempool_octeontx2
diff --git a/drivers/net/octeontx2/meson.build
b/drivers/net/octeontx2/meson.build
index 6cdd036e9..57657de3d 100644
--- a/drivers/net/octeontx2/meson.build
+++ b/drivers/net/octeontx2/meson.build
@@ -5,6 +5,7 @@
sources = files(
'otx2_mac.c',
'otx2_ethdev.c',
+ 'otx2_ethdev_devargs.c'
)
allow_experimental_apis = true
diff --git a/drivers/net/octeontx2/otx2_ethdev.c
b/drivers/net/octeontx2/otx2_ethdev.c
index 08f03b4c3..eeba0c2c6 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -137,6 +137,13 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
+ /* Parse devargs string */
+ rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
+ if (rc) {
+ otx2_err("Failed to parse devargs rc=%d", rc);
+ goto error;
+ }
+
if (!dev->mbox_active) {
/* Initialize the base otx2_dev object
* only if already present
diff --git a/drivers/net/octeontx2/otx2_ethdev.h
b/drivers/net/octeontx2/otx2_ethdev.h
index d9f72686a..f91e5fcac 100644
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -9,11 +9,13 @@
#include <rte_common.h>
#include <rte_ethdev.h>
+#include <rte_kvargs.h>
#include "otx2_common.h"
#include "otx2_dev.h"
#include "otx2_irq.h"
#include "otx2_mempool.h"
+#include "otx2_rx.h"
#define OTX2_ETH_DEV_PMD_VERSION "1.0"
@@ -31,6 +33,8 @@
/* Used for struct otx2_eth_dev::flags */
#define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
+#define NIX_RSS_RETA_SIZE 64
+
#define NIX_TX_OFFLOAD_CAPA ( \
DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
DEV_TX_OFFLOAD_MT_LOCKFREE | \
@@ -56,6 +60,15 @@
DEV_RX_OFFLOAD_QINQ_STRIP | \
DEV_RX_OFFLOAD_TIMESTAMP)
+struct otx2_rss_info {
+ uint16_t rss_size;
+};
+
+struct otx2_npc_flow_info {
+ uint16_t flow_prealloc_size;
+ uint16_t flow_max_priority;
+};
+
struct otx2_eth_dev {
OTX2_DEV; /* Base class */
MARKER otx2_eth_dev_data_start;
@@ -72,12 +85,15 @@ struct otx2_eth_dev {
uint16_t nix_msixoff;
uintptr_t base;
uintptr_t lmt_addr;
+ uint16_t scalar_ena;
uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
uint64_t rx_offloads;
uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
uint64_t tx_offloads;
uint64_t rx_offload_capa;
uint64_t tx_offload_capa;
+ struct otx2_rss_info rss_info;
+ struct otx2_npc_flow_info npc_flow;
} __rte_cache_aligned;
static inline struct otx2_eth_dev *
@@ -96,4 +112,8 @@ int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
+/* Devargs */
+int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
+ struct otx2_eth_dev *dev);
+
#endif /* __OTX2_ETHDEV_H__ */
diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c
b/drivers/net/octeontx2/otx2_ethdev_devargs.c
new file mode 100644
index 000000000..0b3e7c145
--- /dev/null
+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include <inttypes.h>
+#include <math.h>
+
+#include "otx2_ethdev.h"
+
+static int
+parse_flow_max_priority(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+ uint16_t val;
+
+ val = atoi(value);
+
+ /* Limit the max priority to 32 */
+ if (val < 1 || val > 32)
+ return -EINVAL;
+
+ *(uint16_t *)extra_args = val;
+
+ return 0;
+}
+
+static int
+parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+ uint16_t val;
+
+ val = atoi(value);
+
+ /* Limit the prealloc size to 32 */
+ if (val < 1 || val > 32)
+ return -EINVAL;
+
+ *(uint16_t *)extra_args = val;
+
+ return 0;
+}
+
+static int
+parse_reta_size(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+ uint32_t val;
+
+ val = atoi(value);
+
+ if (val <= ETH_RSS_RETA_SIZE_64)
+ val = ETH_RSS_RETA_SIZE_64;
+ else if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)
+ val = ETH_RSS_RETA_SIZE_128;
+ else if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)
+ val = ETH_RSS_RETA_SIZE_256;
+ else
+ val = NIX_RSS_RETA_SIZE;
+
+ *(uint16_t *)extra_args = val;
+
+ return 0;
+}
+
+static int
+parse_ptype_flag(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+ uint32_t val;
+
+ val = atoi(value);
+ if (val)
+ val = 0; /* Disable NIX_RX_OFFLOAD_PTYPE_F */
+
+ *(uint16_t *)extra_args = val;
+
+ return 0;
+}
+
+static int
+parse_flag(const char *key, const char *value, void *extra_args)
+{
+ RTE_SET_USED(key);
+
+ *(uint16_t *)extra_args = atoi(value);
+
+ return 0;
+}
+
+#define OTX2_RSS_RETA_SIZE "reta_size"
+#define OTX2_PTYPE_DISABLE "ptype_disable"
+#define OTX2_SCL_ENABLE "scalar_enable"
+#define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
+#define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
+
+int
+otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev
*dev)
+{
+ uint16_t offload_flag = NIX_RX_OFFLOAD_PTYPE_F;
+ uint16_t rss_size = NIX_RSS_RETA_SIZE;
+ uint16_t flow_prealloc_size = 8;
+ uint16_t flow_max_priority = 3;
+ uint16_t scalar_enable = 0;
+ struct rte_kvargs *kvlist;
+
+ if (devargs == NULL)
+ goto null_devargs;
+
+ kvlist = rte_kvargs_parse(devargs->args, NULL);
+ if (kvlist == NULL)
+ goto exit;
+
+ rte_kvargs_process(kvlist, OTX2_PTYPE_DISABLE,
+ &parse_ptype_flag, &offload_flag);
+ rte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE,
+ &parse_reta_size, &rss_size);
+ rte_kvargs_process(kvlist, OTX2_SCL_ENABLE,
+ &parse_flag, &scalar_enable);
+ rte_kvargs_process(kvlist, OTX2_FLOW_PREALLOC_SIZE,
+ &parse_flow_prealloc_size, &flow_prealloc_size);
+ rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,
+ &parse_flow_max_priority, &flow_max_priority);
+ rte_kvargs_free(kvlist);
+
+null_devargs:
+ dev->rx_offload_flags = offload_flag;
+ dev->scalar_ena = scalar_enable;
+ dev->rss_info.rss_size = rss_size;
+ dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
+ dev->npc_flow.flow_max_priority = flow_max_priority;
+ return 0;
+
+exit:
+ return -EINVAL;
+}
+
+RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
+ OTX2_RSS_RETA_SIZE "=<64|128|256>"
+ OTX2_PTYPE_DISABLE "=1"
+ OTX2_SCL_ENABLE "=1"
+ OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
+ OTX2_FLOW_MAX_PRIORITY "=<1-32>");
diff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h
new file mode 100644
index 000000000..1749c43ff
--- /dev/null
+++ b/drivers/net/octeontx2/otx2_rx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef __OTX2_RX_H__
+#define __OTX2_RX_H__
+
+#define NIX_RX_OFFLOAD_PTYPE_F BIT(1)
+
+#endif /* __OTX2_RX_H__ */
--
2.21.0
