> -----Original Message----- > From: dev <dev-boun...@dpdk.org> On Behalf Of Yongseok Koh > Sent: Friday, January 11, 2019 2:39 AM > To: tho...@monjalon.net > Cc: dev@dpdk.org; shah...@mellanox.com; jer...@marvell.com > Subject: [dpdk-dev] [PATCH v3] config: add Mellanox BlueField ARMv8 SoC > > BlueField is Mellanox's new SoC based on ARMv8. BlueField integrates > Mellanox ConnectX-5 interconnect and Cortex-A72 cores into a single > device. > > http://www.mellanox.com/page/products_dyn?product_family=256&mtag=s > oc_overview > > Signed-off-by: Yongseok Koh <ys...@mellanox.com> > --- > > v3: > * remove redundant mlx5 config items > > v2: > * remove config items which can be used for external PCIe device > > config/defconfig_arm64-bluefield-linuxapp-gcc | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > create mode 100644 config/defconfig_arm64-bluefield-linuxapp-gcc > > diff --git a/config/defconfig_arm64-bluefield-linuxapp-gcc > b/config/defconfig_arm64-bluefield-linuxapp-gcc > new file mode 100644 > index 0000000000..dd252c0e47 > --- /dev/null > +++ b/config/defconfig_arm64-bluefield-linuxapp-gcc > @@ -0,0 +1,18 @@ > +# SPDX-License-Identifier: BSD-3-Clause > +# Copyright 2019 Mellanox Technologies, Ltd > +# > + > +#include "defconfig_arm64-armv8a-linuxapp-gcc" > + > +# Mellanox BlueField > +CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72" > + > +CONFIG_RTE_MAX_NUMA_NODES=1 > +CONFIG_RTE_CACHE_LINE_SIZE=64 > + > +# UMA architecture > +CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n > +CONFIG_RTE_LIBRTE_VHOST_NUMA=n > + > +# PMD for ConnectX-5 > +CONFIG_RTE_LIBRTE_MLX5_PMD=y > -- > 2.11.0
This is ok for make builds, meson build is also required, I think. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
