> -----Original Message-----
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Joyce Kong
> Sent: Thursday, December 13, 2018 3:38 AM
> To: dev@dpdk.org
> Cc: n...@arm.com; Gavin Hu <gavin...@arm.com>; tho...@monjalon.net;
> jerin.ja...@caviumnetworks.com; hemant.agra...@nxp.com;
> honnappa.nagaraha...@arm.com; joyce.k...@arm.com; sta...@dpdk.org
> Subject: [dpdk-dev] [PATCH v1 2/2] rwlock: reimplement with __atomic builtins
>
> From: Gavin Hu <gavin...@arm.com>
>
> The __sync builtin based implementation generates full memory barriers
> ('dmb ish') on Arm platforms. Using C11 atomic builtins to generate one
> way barriers.
>
> Here is the assembly code of __sync_compare_and_swap builtin.
> __sync_bool_compare_and_swap(dst, exp, src);
> 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8]
> 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6]
> 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4]
> 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff
> 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0]
> 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1
> 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4
> <rte_atomic16_cmpset+52> // b.any
> 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0]
> 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0
> <rte_atomic16_cmpset+32>
> 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish
> 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq = none
>
> Fixes: af75078faf ("first public release")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Gavin Hu <gavin...@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>
> Reviewed-by: Ola Liljedahl <ola.liljed...@arm.com>
> Reviewed-by: Joyce Kong <joyce.k...@arm.com>
> Tested-by: Joyce Kong <joyce.k...@arm.com>
> ---
> lib/librte_eal/common/include/generic/rte_rwlock.h | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
Looks ok to me in general, but I think needs to run extra perf testing
to check for regression/correctness on other platforms (obviously IA is my main
concern).
Another thing - my personal preference would be to have it rebased with
'_trylock'
functions also updated - for consistency, plus extra functional tests will be
available for new method.
>
> diff --git a/lib/librte_eal/common/include/generic/rte_rwlock.h
> b/lib/librte_eal/common/include/generic/rte_rwlock.h
> index 5751a0e..51d3aac 100644
> --- a/lib/librte_eal/common/include/generic/rte_rwlock.h
> +++ b/lib/librte_eal/common/include/generic/rte_rwlock.h
> @@ -64,14 +64,14 @@ rte_rwlock_read_lock(rte_rwlock_t *rwl)
> int success = 0;
>
> while (success == 0) {
> - x = rwl->cnt;
> + x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);
> /* write lock is held */
> if (x < 0) {
> rte_pause();
> continue;
> }
> - success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,
> - (uint32_t)x, (uint32_t)(x + 1));
> + success = __atomic_compare_exchange_n(&rwl->cnt, &x, x+1, 1,
As a nit: 'x + 1'
> + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
> }
> }
>
> @@ -84,7 +84,7 @@ rte_rwlock_read_lock(rte_rwlock_t *rwl)
> static inline void
> rte_rwlock_read_unlock(rte_rwlock_t *rwl)
> {
> - rte_atomic32_dec((rte_atomic32_t *)(intptr_t)&rwl->cnt);
> + __atomic_fetch_sub(&rwl->cnt, 1, __ATOMIC_RELEASE);
> }
>
> /**
> @@ -100,14 +100,14 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl)
> int success = 0;
>
> while (success == 0) {
> - x = rwl->cnt;
> + x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED);
> /* a lock is held */
> if (x != 0) {
> rte_pause();
> continue;
> }
> - success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,
> - 0, (uint32_t)-1);
> + success = __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1,
> + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);
> }
> }
>
> @@ -120,7 +120,7 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl)
> static inline void
> rte_rwlock_write_unlock(rte_rwlock_t *rwl)
> {
> - rte_atomic32_inc((rte_atomic32_t *)(intptr_t)&rwl->cnt);
> + __atomic_store_n(&rwl->cnt, 0, __ATOMIC_RELEASE);
> }
>
> /**
> --
> 2.7.4
