+ Bruce
> -----Original Message-----
> From: Gavin Hu <gavin...@arm.com>
> Sent: Monday, December 10, 2018 9:56 PM
> To: dev@dpdk.org
> Cc: tho...@monjalon.net; jerin.ja...@caviumnetworks.com;
> hemant.agra...@nxp.com; Honnappa Nagarahalli
> <honnappa.nagaraha...@arm.com>; Gavin Hu (Arm Technology China)
> <gavin...@arm.com>; sta...@dpdk.org
> Subject: [PATCH v1] config: enable c11 memory model for ARMv8 meson
>
> This patch makes the configuration based on makefile and the configuration
> based on meson to be the same.
>
> Fixes: c6e536e38437 ("build: add more implementers IDs and PNs for ARM")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Gavin Hu <gavin...@arm.com>
> Reviewed-by: Ruifeng Wang <ruifeng.w...@arm.com>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagaraha...@arm.com>
> ---
> config/arm/meson.build | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> 3f91725..dae55d6 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -47,6 +47,7 @@ flags_common_default = [ flags_generic = [
> ['RTE_MACHINE', '"armv8a"'],
> ['RTE_MAX_LCORE', 256],
> + ['RTE_USE_C11_MEM_MODEL', true],
> ['RTE_CACHE_LINE_SIZE', 128]]
> flags_cavium = [
> ['RTE_MACHINE', '"thunderx"'],
> @@ -57,11 +58,13 @@ flags_cavium = [
> ['RTE_USE_C11_MEM_MODEL', false]]
> flags_dpaa = [
> ['RTE_MACHINE', '"dpaa"'],
> + ['RTE_USE_C11_MEM_MODEL', true],
> ['RTE_CACHE_LINE_SIZE', 64],
> ['RTE_MAX_NUMA_NODES', 1],
> ['RTE_MAX_LCORE', 16]]
> flags_dpaa2 = [
> ['RTE_MACHINE', '"dpaa2"'],
> + ['RTE_USE_C11_MEM_MODEL', true],
> ['RTE_CACHE_LINE_SIZE', 64],
> ['RTE_MAX_NUMA_NODES', 1],
> ['RTE_MAX_LCORE', 16],
> --
> 2.7.4
