-----Original Message-----
> Date: Fri, 8 Jun 2018 22:15:11 +0530
> From: Anoob Joseph <anoob.jos...@caviumnetworks.com>
> To: Akhil Goyal <akhil.go...@nxp.com>, Pablo de Lara
> <pablo.de.lara.gua...@intel.com>, Thomas Monjalon <tho...@monjalon.net>
> Cc: Nithin Dabilpuram <nithin.dabilpu...@cavium.com>, Ankur Dwivedi
> <ankur.dwiv...@cavium.com>, Jerin Jacob <jerin.ja...@caviumnetworks.com>,
> Murthy NSSR <nidadavolu.mur...@cavium.com>, Narayana Prasad
> <narayanaprasad.athr...@caviumnetworks.com>, Ragothaman Jayaraman
> <ragothaman.jayara...@cavium.com>, Srisivasubramanian Srinivasan
> <srisivasubramanian.sriniva...@cavium.com>, dev@dpdk.org
> Subject: [PATCH 02/16] crypto/cpt/base: add hardware definitions Cavium CPT
> X-Mailer: git-send-email 2.7.4
>
> From: Nithin Dabilpuram <nithin.dabilpu...@cavium.com>
>
> Adds hardware specific definitions for Cavium CPT device.
>
> Signed-off-by: Ankur Dwivedi <ankur.dwiv...@cavium.com>
> Signed-off-by: Murthy NSSR <nidadavolu.mur...@cavium.com>
> Signed-off-by: Nithin Dabilpuram <nithin.dabilpu...@cavium.com>
> Signed-off-by: Ragothaman Jayaraman <ragothaman.jayara...@cavium.com>
> Signed-off-by: Srisivasubramanian Srinivasan
> <srisivasubramanian.sriniva...@cavium.com>
> ---
> drivers/crypto/cpt/base/cpt_hw_types.h | 836
> ++++++++++++++++++++++++++++++++
> drivers/crypto/cpt/base/mcode_defines.h | 215 ++++++++
> 2 files changed, 1051 insertions(+)
> create mode 100644 drivers/crypto/cpt/base/cpt_hw_types.h
> create mode 100644 drivers/crypto/cpt/base/mcode_defines.h
>
> diff --git a/drivers/crypto/cpt/base/cpt_hw_types.h
> b/drivers/crypto/cpt/base/cpt_hw_types.h
> new file mode 100644
> index 0000000..b4b2af1
> --- /dev/null
> +++ b/drivers/crypto/cpt/base/cpt_hw_types.h
> @@ -0,0 +1,836 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2017 Cavium, Inc
> + */
> +
> +#ifndef __CPT_HW_TYPES_H
> +#define __CPT_HW_TYPES_H
> +
> +#include <stddef.h>
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <errno.h>
> +#include <string.h>
Use alphabetical order.
> +
> +#define CPT_INST_SIZE (64)
> +#define CPT_VQ_CHUNK_ALIGN (128) /**< 128 byte align */
> +#define CPT_NEXT_CHUNK_PTR_SIZE (8)
> +#define CPT_INST_CHUNK_MAX_SIZE (1023)
> +
> +#define CPT_PF_VF_MAILBOX_SIZE (2)
> +
> +#define CPT_VF_INTR_MBOX_MASK (1<<0)
> +#define CPT_VF_INTR_DOVF_MASK (1<<1)
> +#define CPT_VF_INTR_IRDE_MASK (1<<2)
> +#define CPT_VF_INTR_NWRP_MASK (1<<3)
> +#define CPT_VF_INTR_SWERR_MASK (1<<4)
> +#define CPT_VF_INTR_HWERR_MASK (1<<5)
> +#define CPT_VF_INTR_FAULT_MASK (1<<6)
> +
> +/*
> + * CPT_INST_S software command definitions
> + * Words EI (0-3)
> + */
> +typedef union {
> + uint64_t u64;
> + struct {
> + uint16_t opcode;
> + uint16_t param1;
> + uint16_t param2;
> + uint16_t dlen;
> + } s;
> +} vq_cmd_word0_t;
> +
> +typedef union {
> + uint64_t u64;
> + struct {
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
Use DPDK primitives for endian checking.
> + uint64_t grp : 3;
> + uint64_t cptr : 61;
> +#else
> + uint64_t cptr : 61;
> + uint64_t grp : 3;
> +#endif
> + } s;
> + uint8_t reg_A[8];
> + uint8_t ci_key[16];
> +} mc_kasumi_ctx_t;
> +
> +#define ENC_CTRL(fctx) fctx.enc.enc_ctrl.e
> +#define AUTH_CTRL(fctx) fctx.auth.auth_ctrl
> +#define P_ENC_CTRL(fctx) fctx->enc.enc_ctrl.e
> +
> +#define MAX_IVLEN 16
> +#define MAX_KEYLEN 32
If something specific to CPT, IMO, better to start with CPT_ to
avoid name collision.
