27/11/2013 15:06, Dmitry Vyal :
> Looks like I finally found the reason. After applying this patch I can
> no longer reproduce the error.
>
> --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
> +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
> /* Wait for AN to leave state 0 */
> - for (i = 0; i < 10; i++) {
> + for (i = 0; i < 100; i++) {
> msec_delay(4);
> anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
> if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
It's probably due to a frequency scaling.
The timer based is initialized when DPDK initialize
and the CPU can change its frequency, breaking next timers.
The fix is to control the CPU frequency.
Please try this, without your patch:
for g in /sys/devices/system/cpu/*/cpufreq/scaling_governor; do echo
performance >$g; done
The right fix for applications (examples and testpmd included)
could be to call rte_power_init(). Patches are welcomed.
Thank you for your analysis
--
Thomas
