On Wed, 05 Jun 2013 20:05:15 +0200 Damien Millescamps <damien.millescamps at 6wind.com> wrote:
> On 06/05/2013 05:49 PM, Stephen Hemminger wrote: > > On Wed, 05 Jun 2013 16:50:03 +0200 > > Damien Millescamps <damien.millescamps at 6wind.com> wrote: > > > >> Hi Stephen, > >> > >> Overall this patch is very nice. My only comment on this one is why do > >> you limit the max number of memory resources to 5 ? > >> The PCI configuration space permits to store up to 6 base addresses. > >> > >>> +#define PCI_MEM_RESOURCE 5 > >> Please, can you add a log/comment with your patch, too ? > >> > >> > >> Cheers, > > Only because I was trying to save some space, and I didn't see any hardware > > with that many useful regions. Also the kernel UIO driver has some control > > over which regions get exposed. > > I agree that hardware generally don't use that much BAR for the PCIe. > However, this is only a matter of 20 to 24 Bytes, so I don't see any > reason not defining this macro as per the PCI standard value. > > Could you add a commit log and change that so it can be ack'd and pushed > in the DPDK repository ? > > Thanks, Go ahead and change the 5 to a 7. No point in another resend of whole pile.
