On Thu, Jul 19, 2001 at 03:38:44AM -0400, Christopher C. Chimelis wrote:
>
> On Thu, 19 Jul 2001, Stephen Frost wrote:
>
> > > Ryan Murray reported to me that a 4.1 compile on mips fails.
> >
> > This is an update to this issue.
> >
> > After adding another parameter to RANGE ('0' for pci domain) and
> > attempting to compile I ran into a few other problems. First
> > off, write_mem_barrier was undefined under MIPS. After looking
> > at some other archs I went ahead and defined it for MIPS as:
> >
> > #define write_mem_barrier /* NOP */
>
> Double-check your arch manual. At least on alpha, we have a memory
> barrier instruction that's not a nop (and alpha is similar to mips in some
> ways, so I'd verify that). I have an R4400 manual around here
> somewhere...if I get time, I'll look for it and look it up as well.
This is what the kernel does for non write-back-caches:
#define mb() \
__asm__ __volatile__( \
"# prevent instructions being moved around\n\t" \
".set\tnoreorder\n\t" \
"# 8 nops to fool the R4400 pipeline\n\t" \
"nop;nop;nop;nop;nop;nop;nop;nop\n\t" \
".set\treorder" \
: /* no output */ \
: /* no input */ \
: "memory")
#define rmb() mb()
#define wmb() mb()
So IMHO this is the way to go for non wb cpus. For wb cpus the kernel
flushes the caches, but calls this "overly paranoid" anyway.
-- Guido
