On Fri, Apr 21, 2006 at 07:06:13AM +1000, Benjamin Herrenschmidt wrote: > Unfortunately, he has to do things a bit differently. He can't afford to > have the kernel BAT mapping cover his non-cacheable pages. Thus he needs > a reserved pool. Last I looked at our coherent code, it didn't reserve > memory at all, just address space, thus assuming the CPU can handle > having both a caheable and a non-cacheable mapping of the same pages... > (On 6xx this is deadly even if you don't access those cacheable pages > because the CPU prefetch may do it for you).
Ben, is this _real_ problem on 6xx or just a theory? Does 6xx actually prefetch beyond page boundary? So far, all "prefetching" I saw which broke non-coherent DMA was not due to the CPU doing prefetching, but _software_ prefetching being too aggressive. -- Eugene -- To UNSUBSCRIBE, email to [EMAIL PROTECTED] with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
