On Fri, Apr 21, 2006 at 12:08:18AM +0200, Gerhard Pircher wrote: > > --- Ursprüngliche Nachricht --- > > Von: Eugene Surovegin <[EMAIL PROTECTED]> > > An: Gerhard Pircher <[EMAIL PROTECTED]> > > Kopie: [EMAIL PROTECTED], debian-powerpc@lists.debian.org > > Betreff: Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed > > Datum: Thu, 20 Apr 2006 14:55:14 -0700 > > > > Well, you aren't the first person who tries to run G4 with > > CONFIG_NOT_COHERENT_CACHE. This was done before and I don't remember > > that those people had to implement anything as complex as you are > > trying to do. > > Maybe these systems have cache coherent northbridges, which is not the case > for the AmigaOne and its "famous" ArticiaS northbridge.
Nope. I believe Eugene is referring to the Marvell 64x60 line of *North* bridges. > > You can try asking on #mklinux. It always better to ask people who > > actually _did_ this :). > > > > In fact, I just grepped 2.6 and found > > #ifdef(CONFIG_NOT_COHERENT_CACHE) in syslib/mv64x60.c. Guess what > > systems usually have this type of bridge? Not 4xx/8xx, that's for sure. > > Hmm, strange. AFAIK the NOT_COHERENT_CACHE config option is available only > for the 4xx and 8xx platforms. Wouldn't the config option depend on > CONFIG_6XX too, if there are not cache coherent systems with G4 cpus? > > At least I could not compile in the dma-mapping.c file without modifying the > Kconfig file. If you're looking in arch/ppc/Kconfig in either the kernel.org or paulus' git trees, look further down. There is a separate option where NOT_COHERENT_CACHE can be set for 64x60 bridges. Mark -- To UNSUBSCRIBE, email to [EMAIL PROTECTED] with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
