>Right, but with a catch: the DMA transfer must complete before the image can >displayed. Right now, this is ensured by waiting for the DMA engine to go >idle, >which is basically implemented as a busy loop in the DRM. So while the >transfer >will be faster than with plain memcpy, a lot of CPU cycles are wasted.
Whiwh seems silly. What should happen is - Decode frame 1 - Start DMA'ing frame 1 - Decode frame 2 - Queue DMA for frame 2 (or start DMAing if fame 1 is done) - Wait for frame 1 to complete DMA - Display frame 1 - Decode frame 3 etc... That is you should have at least 2 buffers so you can asynchronously DMA a frame while decoding the next frame. It makes only sense to busy loop on the DMA if you are decoding faster than what you display. If this is not the case, then you are just throwing CPU cycles by the window. The whole point of DMA is for the CPU to do something else while the ATI chip is doing the transfer. Ben. -- To UNSUBSCRIBE, email to [EMAIL PROTECTED] with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
