John Steele Scott <[EMAIL PROTECTED]> wrote: > --=-=-= > > Joerg Sommer <[EMAIL PROTECTED]> writes: >> Hi, >> >> inspired by John Steele (<[EMAIL PROTECTED]>, >> <news:[EMAIL PROTECTED]>) I searched a little bit with google >> and found that the instruction cache throttling register is named in the >> Kernel source (include/asm-ppc/reg.h). A todo note is made in >> arch/ppc/kernel/temp.c. >> >> I here next semester a lecture about kernel hacking. My idea is to >> implements the instruction cache throttling register in this lecture. Are >> there any plans to do this? Should there be a new node in >> /sys/devices/system/cpu/cpu?/ to control the contents of the register? Is >> there any similar at any other platform? > > I don't think there should be a new node to control the register; it should be > done through the cpufreq mechanism. You can get a start by reading the
Do you mean the powersave governor should controll this register too? > I'm interested to discuss this more. I have been wanting this feature for a > while; and even have written some code for it a couple of times, but I tend to > get distracted too easily when it comes to hobby code. Is your code anywher available? Jörg. -- Hügelschäfer's Law (http://www.bruhaha.de/laws.html): Beiträge werden dort gepostet, wo sie den größten Widerstand hervorrufen. -- To UNSUBSCRIBE, email to [EMAIL PROTECTED] with a subject of "unsubscribe". Trouble? Contact [EMAIL PROTECTED]
