Hi Ben,
On Wed, Jul 29, 2026 at 11:36:21AM -0400, Ben Hearsum wrote:
> I will take a closer look, but a quick search seems to suggest that
> https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16098 is the
> same issue.
Thanks for the investigation/search. That would be 062499cc4813
("drm/i915/mtl+: Enable PPS before PLL") which landed in v7.2-rc1. The
commit is queued as well for the next 7.1.y update, I'm attaching the
patch here. If you are up to additonally test a patched kernel with
that patch on top, to confirm it fixes your issue as well that would
be great.
Instructions on how to do it are at:
https://kernel-team.pages.debian.net/kernel-handbook/ch-common-tasks.html#id-1.6.6.4
Regards,
Salvatore
>From 062499cc4813b5a3cbed5dd4fbe0177265858450 Mon Sep 17 00:00:00 2001
From: Imre Deak <[email protected]>
Date: Fri, 12 Jun 2026 20:26:17 +0300
Subject: drm/i915/mtl+: Enable PPS before PLL
MIME-Version: 1.0
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Content-Transfer-Encoding: 8bit
From: Imre Deak <[email protected]>
commit 062499cc4813b5a3cbed5dd4fbe0177265858450 upstream.
Enabling PPS after a display port's PLL is enabled leads to PLL / DDI
BUF timeouts during system resuming after a long (> 45 mins) suspended
state, at least on some ARL and MTL laptops, either all or some of them
also containing an Nvidia GPU. Enabling PPS first and then the PLL fixes
the problem for all the reporters.
A similar issue is seen when enabling an external DP output on PHY B
(vs. PHY A in the above eDP cases), where this change will not have any
effect (since no PPS is used in that case). There isn't any direct
connection between PPS and PLL, so the fix for eDP works by some
side-effect only. However Bspec does seem to require enabling PPS first,
so let's do that. Further investigation continues on the actual root
cause and a cure for external panels.
Fixes: 1a7fad2aea74 ("drm/i915/cx0: Enable dpll framework for MTL+")
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16098
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16064
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16042
Cc: Mika Kahola <[email protected]>
Cc: [email protected] # v7.0+
Tested-by: Jouni Högander <[email protected]>
Tested-by: Marco Nenciarini <[email protected]>
Reviewed-by: Suraj Kandpal <[email protected]>
Signed-off-by: Imre Deak <[email protected]>
Link: https://patch.msgid.link/[email protected]
(cherry picked from commit 28783a274e886dd6da61419be6020bd9d0384e9f)
Signed-off-by: Rodrigo Vivi <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2652,9 +2652,6 @@ static void mtl_ddi_pre_enable_dp(struct
/* 3. Select Thunderbolt */
mtl_port_buf_ctl_io_selection(encoder);
- /* 4. Enable Panel Power if PPS is required */
- intel_pps_on(intel_dp);
-
/* 5. Enable the port PLL */
intel_ddi_enable_clock(encoder, crtc_state);
@@ -3710,6 +3707,14 @@ intel_ddi_pre_pll_enable(struct intel_at
else if (display->platform.geminilake || display->platform.broxton)
bxt_dpio_phy_set_lane_optim_mask(encoder,
crtc_state->lane_lat_optim_mask);
+
+ /*
+ * There is no direct connection between the PLL and PPS, however
+ * enabling PPS before PLL is required to avoid PLL/DDI BUF timeouts
+ * during system resume. Do that matching the Bspec order as well.
+ */
+ if (DISPLAY_VER(display) >= 14)
+ intel_pps_on(&dig_port->dp);
}
static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
