https://share.google/aimode/5A6WShOlcKlA3QCpi
has anybody connected the qspi flash to the rp2040 via a breadboard using breakouts as a learning or prototyping exercise Yes, enthusiasts have connected QSPI flash to the RP2040 on a breadboard for learning and prototyping purposes . This is a natural exercise because the bare RP2040 chip, unlike the pre-assembled Raspberry Pi Pico board, has no on-chip flash memory and relies on an external QSPI flash for program storage. Building a custom RP2040 circuit on a breadboard can be challenging but is an effective way to learn about its hardware requirements. Key components for this project often include: A minimal RP2040 breakout board: Since the RP2040 uses a surface-mount QFN-56 package, a breakout board is necessary to make the pins breadboard-compatible. Projects like the "Minimal RP2040 Board" demonstrate this exact setup. A QSPI flash breakout board: The flash memory chip also comes in a surface-mount package. Companies like Adafruit offer QSPI flash breakout boards that convert the SOIC package to a breadboard-friendly DIP layout, making it easier to prototype. Supporting circuitry: A working RP2040 circuit on a breadboard requires a 3.3V power supply and a crystal oscillator. An integrated voltage regulator is also needed to produce the 1.1V supply for the chip's digital core. A typical breadboard setup Mount the breakouts: The RP2040 and QSPI flash breakout boards are placed on the breadboard. Make connections: Wires are used to connect the QSPI pins on the RP2040 breakout to the corresponding pins on the flash breakout. These connections must be kept short to minimize signal degradation. Add support components: The required power supplies, decoupling capacitors, and the crystal oscillator are added to the breadboard. Connect for programming: The breadboard circuit needs a way to be programmed. One method is to use a USB connector and circuitry for the drag-and-drop UF2 bootloader functionality. Alternatively, a second RP2040 board acting as a "Picoprobe" can be used for debugging and programming via the SWD interface. Key considerations and challenges Trace impedance: The high-speed QSPI signals are best with short, clean connections. While a breadboard works for low-speed prototyping, it is not ideal for the high-speed QSPI bus. This is why official documentation recommends direct, short connections for custom PCBs. Bootloader activation: To load a new program onto the external flash, the RP2040 must be put into bootloader mode. This is done by holding down the BOOTSEL button (or shorting the QSPI_SS pin to ground) during a reset. Initial program load: The RP2040's ROM bootloader handles the initial loading of a program from the QSPI flash. An external programming method, like a Picoprobe or the built-in UF2 bootloader via USB, is used for the very first program upload. Example projects and tutorials Technoblogy's Minimal RP2040 Board: This project details the design and assembly of a bare-bones RP2040 circuit specifically intended for use on a prototyping board. Adafruit QSPI DIP Breakouts: Adafruit provides tutorials for using their breadboard-compatible flash breakouts, which can be adapted for a custom RP2040 circuit. Custom RP2040 PCBs: Many enthusiasts document their custom RP2040 PCB designs on forums like Reddit and EEVblog, providing valuable insights into the required circuitry, even if they aren't breadboard-based. can you find any existing boards for the rp2040 or a similar chip (I’m looking to bit-bang USB or such) that don’t include flash on the board, or at least use a socket Several minimal RP2040 and alternative microcontroller boards cater to your need for external QSPI flash memory, often found in smaller or "bare" breakout form factors . For bit-banging USB, a RISC-V board like the CH32V003 is also a strong contender due to its low cost and vibrant maker community. Minimal RP2040 breakout boards PGA2040 : This small, square breakout board from The Pi Hut is designed for embedded projects with a minimal footprint. It includes only the core components needed to run the RP2040 , such as the crystal oscillator and voltage regulator, and has an unpopulated USB connector. This requires you to add your own external QSPI flash module. Minimal RP2040 Board (Technoblogy): As discussed previously, this DIY project demonstrates how to build your own bare-bones RP2040 circuit. The design includes connections for an external flash chip and exposes the necessary pins, making it ideal for learning and experimentation. Waveshare RP2040-Tiny : This very small board moves the USB and boot buttons to an optional separate board, leaving only the essential parts on the main PCB. While it usually comes with flash, its diminutive size is built around a similar philosophy of minimal on-board components. PGA2040 RP2040 Breakout Board PIM577 $8.75 4.9(15) RP2040Zero Mini PICO Board with RP2040, DualCore M0, 2MB Flash, USBC Waveshare RP2040-Zero Board with Pin Header Based on Raspberry Pi MCU RP2040 $44.89 5.0(2) waveshare RP2040-Plus with Header, Pico-Like MCU Board Based on Raspberry Pi RP2040 Chip, Dual-core Arm Processor, Onboard 4MB Flash, USB-C Connector, $28.99 RISC-V microcontroller boards The RP2040's native USB support makes it a more common choice for USB projects, but other chips without integrated USB are deliberately chosen for bit-banging exercises. CH32V003 boards: For maximum control over the USB interface, some projects use the ultra-low-cost CH32V003 RISC-V microcontroller. It lacks native USB support, requiring a bit-banged implementation. Many development boards for this chip are readily available and focus on exposing GPIO pins for custom projects. Bit-banging USB with a CH32V003 is a popular project within the electronics hobbyist community. How to adapt boards with pre-soldered flash If you can't find a board without flash, it's possible to desolder the chip. However, this is a delicate operation that requires proper tools and a high level of expertise to avoid damaging the board. Select a compatible board: Look for a board where the flash chip is relatively easy to access. Remove the chip: Use a hot air rework station or specialized solder tools to carefully remove the surface-mount flash memory. Prepare your new connection: The QSPI flash pads will now be exposed, allowing you to solder on wires or a custom breakout for your own external flash solution. can I program the CH32V003 using open hardware? Yes, you can program the CH32V003 using open hardware . While the microcontroller's single-wire debug (SDI) interface is a proprietary protocol developed by the manufacturer WCH, the open-source community has developed multiple solutions that work with open hardware platforms. Open-hardware programmers The most prominent open-hardware solution for programming the CH32V003 uses a Raspberry Pi Pico. PicoRVD: This open-source project runs on a Raspberry Pi Pico and acts as a GDB-compatible remote debug interface for the CH32V003. Functionality: PicoRVD replaces the need for the proprietary WCH-Link dongle by using the Pico's Programmable I/O (PIO) to bit-bang the single-wire debug protocol. Hardware requirements: You only need a Raspberry Pi Pico and a single pull-up resistor to connect to the CH32V003. Software requirements: You can debug and flash your CH32V003 with the gdb-multiarch debugger and the ch32v003fun open-source library. My alpha Pico-based CH32V003 debug tool is ready for a few ... Apr 26, 2023 — The CH32V003 is a 10-cent RISC-V microcontroller with a proprietary single-wire debug interface and a corresponding proprietary debug dongle + modified version ... Hacker News aappleby/picorvd: GDB-compatible RISC-V ... - GitHub PicoRVD. This repo contains a GDB-compatible remote debug interface for the RISC-V based CH32V003 series of chips by WinChipHead. It allows you to program and d... GitHub Open-source software toolchains Even if you use the official WCH-LinkE hardware programmer, you can still develop using entirely open-source software and development tools. ch32v003fun: This is a minimal, open-source development kit created by CNLohr. It provides headers and examples that avoid WCH's heavy HAL (Hardware Abstraction Layer), allowing for very small and efficient code. minichlink: This open-source tool, also from CNLohr, enables cross-platform communication with the CH-Link programmer via libusb. RISC-V GCC toolchain: An open-source GCC compiler for RISC-V targets is essential for compiling your code. rvprog: This is a platform-independent, open-source command-line tool written in Python for uploading firmware binaries. Alternative (partially open) approach For a different workflow, you can program the chip over UART if it has a specific bootloader installed. The manufacturer provides a method to program a UART-based bootloader onto the chip using the official WCH-LinkE hardware. After the bootloader is installed, the ch32v003-uart-programmer tool (available on GitHub) can be used to flash new firmware over a standard UART connection. This approach still requires the proprietary WCH-LinkE for the initial bootloader flash, making it not fully open hardware. is anybody programming the CH32V003 with another CH32V003? what’s the cheapest solution to go open-silicon or ttl/discrete/fogs with usb bit-banging here? Programming a CH32V003 with another CH32V003 Yes, the open-source community has developed projects to program one CH32V003 with another. This is part of the broader effort to move away from proprietary tools and embrace open hardware. The process leverages the open-source tooling like ch32fun and typically involves: One CH32V003 acts as the programmer by bit-banging the proprietary SDI protocol. It is connected to the other CH32V003, which is the target being programmed. This approach is primarily a hobbyist or learning exercise, as it requires more manual setup than using an off-the-shelf programmer like a Raspberry Pi Pico with PicoRVD. aappleby/picorvd: GDB-compatible RISC-V ... - GitHub PicoRVD. This repo contains a GDB-compatible remote debug interface for the RISC-V based CH32V003 series of chips by WinChipHead. It allows you to program and d... GitHub GitHub - cnlohr/ch32fun An open source development environment (tooling, headers, examples) for the CH32V003 (and many other riscv chips made by WCH) with gcc-riscv64 that can be used ... GitHub Cheapest open-silicon or logic-based solution for USB bit-banging If the goal is to perform USB bit-banging with the most minimal and open hardware possible, your options depend on whether you prioritize open-silicon or purely discrete/FPGA logic. Open-silicon solution: CH32V003 with ch32v003fun The CH32V003 microcontroller itself is one of the cheapest and most accessible ways to achieve USB bit-banging. Cost: The CH32V003 chip can cost as little as $0.10 in bulk, making it the lowest-cost path. Tooling: The ch32v003fun open-source library provides the necessary code and examples to implement a low-speed software USB stack, which is what allows for the bit-banging over GPIO. Setup: You will need to build the supporting circuitry for the CH32V003, including a clock and power supply, on a breadboard or small PCB. Discrete/logic gate solution: not viable for USB bit-banging Bit-banging a complex, high-speed protocol like USB using discrete TTL or other simple logic gates is not a realistic or cheap approach. Speed: Low-speed USB operates at 1.5 Mbps, and discrete logic would be unable to provide the precise timing required for clock recovery and data handling. Complexity: A functional discrete-logic USB implementation would require a massive number of gates to manage the state machine, packet encoding/decoding, and error checking. Cost: The sheer number of discrete components would make this solution far more expensive than any microcontroller. FPGA solution: feasible but more expensive and complex An FPGA offers the speed and reconfigurability to implement a USB stack, but it is not the cheapest solution. Cost: An FPGA, even a low-cost one, costs significantly more than a CH32V003. Setup: The setup is more complex, requiring knowledge of HDLs like VHDL or Verilog, and a programmer for the FPGA itself. Benefit: An FPGA provides full control over the hardware logic and is an excellent learning tool for digital design. Example: You can find examples of bit-banged USB implementations on platforms like the Lattice iCE40, which is supported by open-source toolchains. Summary: Cheapest approach The cheapest and most accessible path to USB bit-banging using open-source tools is with the CH32V003 and the ch32v003fun library. The CH32V003 chip is inexpensive, and the community has built a robust open-source ecosystem around it. The hardware setup is minimal, and the software is freely available and well-documented. ok, but say I want a bunch of cheap fpgas lying around instead of CH32V003s, what product would I be looking at? what is everybody using? For hobbyists seeking inexpensive FPGAs, the most popular and readily available products are based on Lattice iCE40 and Gowin FPGAs. The Sipeed Tang Nano series is a common recommendation for newcomers due to its low cost and supporting ecosystem built by the open-source community. Popular low-cost FPGA boards Sipeed Tang Nano series (Gowin FPGAs) The Sipeed Tang Nano boards are a favorite among hobbyists for their very low prices, with models often costing under $30. Sipeed Tang Nano 9K: A frequently recommended board for beginners, featuring a Gowin GW1N-9 FPGA with 8,640 Look-Up Tables (LUTs). It includes onboard USB-JTAG and USB-UART, making it easy to get started with basic projects. Open-source toolchain: The Gowin FPGAs on these boards are well-supported by the open-source toolchain apicula and nextpnr, which work with the more universal synthesis tool Yosys. TinyFPGA boards (Lattice iCE40) The TinyFPGA project was instrumental in popularizing low-cost, open-source FPGA development for hobbyists. The tiny form factor boards, such as the TinyFPGA BX, are breadboard-friendly and have a thriving community. TinyFPGA BX: Features a Lattice iCE40LP8K FPGA and includes a built-in USB programmer. This board is fully supported by the Project IceStorm open-source toolchain, a major milestone in open FPGA tooling. Open-source toolchain: The Lattice iCE40 family is famous for being the first FPGA series with a fully reverse-engineered, open-source toolchain (Project IceStorm), making it an excellent choice for those who prioritize open silicon. Fomu (Lattice iCE40) For projects that need to be as small as possible, Fomu is a programmable FPGA that fits inside a USB port. It is also based on a Lattice iCE40 FPGA. Features: Fomu's main selling point is its size and convenience. It features an RGB LED and four buttons, runs a RISC-V core on its FPGA, and supports a fully open-source toolchain. Factors to consider When choosing an FPGA, especially for USB bit-banging, keep these things in mind: Resource availability: A low-speed (1.5 Mbps) USB stack can be bit-banged with fewer resources, but a full-speed (12 Mbps) stack requires more logic and precise timing. The higher-end boards in the Tang Nano and TinyFPGA BX lineup have enough resources for full-speed USB. Toolchain maturity: Both the iCE40 and Gowin toolchains are functional, but the Project IceStorm toolchain for Lattice FPGAs is considered more mature and stable, having been around longer. Onboard features: For ease of use, boards like the Tang Nano 9K often include more helpful peripherals, such as onboard USB-JTAG for programming and a USB-UART bridge for communication. USB bit-banging: Projects like the ulixxe/usb_cdc library on GitHub specifically target FPGAs like the TinyFPGA-BX to perform bit-banged USB communication, showing the feasibility of your goal with these boards. want multiple usb ports, does the fomu work? what is each product’s price? I found the mist/mister community and work is pretty large — is there a large community for a cheaper fpga? Multiple USB ports with Fomu The Fomu is not designed to support multiple USB ports on its own. It fits inside a single USB Type-A port, and its primary purpose is as a learning and prototyping tool for FPGA and RISC-V development. To achieve multiple USB ports, you would need to implement a USB hub protocol in your FPGA design, which would be an extremely complex task. For multiple USB ports on a budget, it is far more practical to use a dedicated USB hub chip with a cheap FPGA. Cheaper FPGA boards and prices Here is a breakdown of the prices for some of the common low-cost FPGA boards mentioned: Product Typical PriceFPGA ChipKey Features Sipeed Tang Nano 9K~$20Gowin GW1N-98.6K LUTs, HDMI, RGB, SPI, onboard USB-JTAG and USB-UART. Sipeed Tang Nano 20K~$30–$40Gowin GW2A-18More LUTs (18K) and SDRAM for more complex projects. TinyFPGA BX~$50Lattice iCE40LP8K8K LUTs, breadboard-friendly, open-source toolchain (Project IceStorm), built-in USB programmer. Fomu~$45–$50Lattice iCE40UP5KFits in a USB port, RISC-V core capable, includes touch buttons and RGB LED. Note: Prices vary significantly based on retailer (e.g., AliExpress, Adafruit), shipping, and demand. Cheap FPGA community vs. MiSTer While the MiST/MiSTer communities are very active, they focus on a specific, niche area: retro video game and computer emulation. Because MiSTer requires more capable, and therefore more expensive, FPGAs to run its cores, its community is a separate branch of the broader FPGA hobbyist scene. For the cheapest FPGAs, such as the Sipeed Tang Nano and TinyFPGA series, the community is focused on: Open-source tooling: A major driving force is the development and use of entirely open-source toolchains like Yosys, nextpnr, and Project IceStorm, which have been built from the ground up by the community. Custom hardware: Hobbyists design and build their own custom boards for specific applications, ranging from simple logic circuits to complex custom CPUs. Learning and education: Many resources, including tutorials and example projects, are created specifically for newcomers to learn FPGA fundamentals without the need for expensive, proprietary tools. This community is primarily found on online forums and platforms like: Reddit: Subreddits such as r/FPGA and r/GowinFPGA have regular discussions about cheap boards and projects. EEVblog Forum: The forum has extensive threads dedicated to low-cost FPGA boards and toolchain discussions. Hackster.io and Instructables: These platforms host numerous projects and tutorials using cheap FPGAs for a variety of tasks. GitHub: Many of the open-source tools and design files for these boards and their projects are maintained on GitHub. is there a collection of many designs somewhere like with mist/mister? For low-cost and open-source FPGAs like those from Lattice and Gowin, there is no single, centralized, and curated collection of designs equivalent to the MiSTer project. The community is more fragmented, reflecting its hobbyist roots and focus on diverse applications beyond retro gaming. However, many projects and resources are available on collaborative platforms. GitHub repositories GitHub is the primary hub for open-source FPGA designs. Developers often create and maintain their own project repositories, and a few "awesome list" collections attempt to curate these resources. Vitorian/awesome-fpga: This list is a great starting point for finding resources, including tutorials, languages, and project ideas. os-fpga/open-source-fpga-resource: This repository specifically tracks open-source projects related to FPGA infrastructure and development, including toolchains like F4PGA and OpenFPGA. Individual board repositories: You can find many example designs and templates within the official GitHub pages for specific boards. For example, the tinyfpgaorganization page hosts bootloaders, board files, and example projects for the TinyFPGA series. Vitorian/awesome-fpga: A collection of resources on ... - GitHub Awesome FPGA. A collection of resources on FPGA devices and development in general. We want students and professionals to be able to grasp the world of FPGA fro... GitHub TinyFPGA - GitHub Aug 22, 2024 — Popular repositories * TinyFPGA-Bootloader Public. An open source USB bootloader for FPGAs. AGS Script 368 92. * TinyFPGA-BX Public. AGS Script 282 95. * TinyFP... GitHub Project-focused websites and forums Many projects are hosted on personal websites, technical forums, and community hubs. Hackster.io and Instructables: These sites showcase a wide variety of FPGA projects, often including step-by-step instructions and all the necessary code and schematics. You can search these sites specifically for projects using low-cost boards like the Tang Nano or TinyFPGA. EEVblog Forum: The electronics engineering community on the EEVblog forum frequently discusses projects related to cheap FPGAs, including design challenges and solutions. Reddit: Subreddits like r/FPGA and r/GowinFPGA are active communities where people share and troubleshoot projects. A Reddit thread, for example, lists various retro gaming projects available for the Tang Nano boards. LiteX ecosystem For System-on-Chip (SoC) projects, the LiteX ecosystem provides a collaborative environment for building FPGA designs. What it is: LiteX is a Python-based framework that helps automate the process of creating complex SoC designs for FPGAs. It supports various open hardware platforms, including low-cost boards. What it offers: LiteX provides ready-to-use IP cores for things like CPU cores (including RISC-V), memory controllers, and USB interfaces, making it easier to build and share complex designs. Key differences from MiSTer Unlike the MiSTer community, the cheap FPGA ecosystem is more fragmented and focused on fundamental hardware experimentation rather than a single, shared application. This makes finding specific designs more of a search-and-discover process, but it also reflects a wider variety of project types. I’d like to do usb proxying and bit-banging without a hub. any existing tools? will facedancwr work on fomu? USB proxying without a hub USB proxying without a hub on a single FPGA like the Fomu is not possible. USB proxying requires a system that can act as both a USB host (to talk to the connected device) and a USB device (to talk to the host computer). A standard FPGA like the iCE40UP5K on the Fomu has no hardware for USB host capabilities. Any project attempting a USB proxy with a single device would need a chip with both a host and a device controller, such as some ARM boards or complex System-on-Chip (SoC) solutions. On a cheap FPGA, a USB proxy is usually implemented with an external USB controller IC. FaceDancer on Fomu Yes, the FaceDancer framework can work on a Fomu, but only to act as a USB devicefor bit-banging and fuzzing purposes. The libusb library, which is a component of the FaceDancer framework, is used to communicate with the hardware, including the Fomu. An open-source, Amaranth-based hardware stack called Luna was developed to provide an alternative to the FaceDancer hardware. It is important to understand the limitation: The Fomu's single USB port can only emulate a device, not a host. This means you can: Emulate and fuzz different USB devices. Proxy traffic on the device side (emulating a malicious or altered device). However, you cannot use it to proxy traffic from a downstream device. Tools for USB bit-banging and proxying Here are some of the tools and ecosystems used for this kind of work: Luna: A powerful, open-source USB toolkit for hardware built with the Amaranth HDL framework. It enables you to use FPGAs to build complex USB devices, including custom fuzzing targets and test platforms. Facedancer: While originally associated with specific hardware, the framework has evolved to support other backends, including Luna. LiteX: A Python-based SoC builder for FPGAs. It provides IP cores that can help with USB interfacing and other complex hardware designs. Renode: A tool for simulating virtual hardware, including the Fomu. This can be a useful tool for software development and debugging of USB device firmware. Wireshark with usbmon: For any USB proxying or bit-banging project, you'll want to use software tools to analyze the USB traffic. Wireshark, with the usbmon driver, is the standard for sniffing and analyzing USB packets. Nono, I want to be simple, down on the wire. I wouldn’t use a controller unless it was fpga’d Building a USB proxy by bit-banging with two FPGAs is a challenging but achievable "down on the wire" approach . You would dedicate one cheap FPGA to act as the host and another to act as the device. The Luna framework is the leading open-source project for this type of advanced, deep-level USB work on FPGAs. Design with two cheap FPGAs This design avoids dedicated USB controller ICs by implementing the USB stack entirely in FPGA logic using the Luna framework. FPGA #1 (The Host): This FPGA will communicate with the upstream host computer (e.g., your PC). Its gateware would implement a USB device role. It would listen to the host computer, process commands, and potentially alter the data before sending it to the second FPGA. FPGA #2 (The Device): This FPGA would communicate with the downstream USB peripheral (e.g., a flash drive or keyboard). Its gateware would implement a USB hostrole. It would power the peripheral, enumerate it, and receive/send data to it. The "Wire": A physical connection between the two FPGAs would be needed for them to communicate. This could be a simple serial connection or a more complex high-speed protocol like SPI or a direct parallel bus. This connection is where you would implement your proxying logic, allowing you to observe, block, or modify traffic between the two USB links. Using Luna and Fomu The Luna framework is the ideal choice for this project. Fomu as a USB device: While a single Fomu can only act as a USB device, using two separate boards in a "man-in-the-middle" setup would achieve your goal. Hardware and Gateware: Luna provides all the necessary components for implementing the USB logic, including gateware for the device-side and host-side stacks. Tooling: Luna is built on the Amaranth HDL framework, which integrates with Yosys and other open-source tools. An example: Cynthion For advanced projects like this, some people use a more capable platform like Cynthion, also from the developers of Luna. While not the "cheapest" option, it is a purpose-built piece of open hardware for USB experimentation. Features: It contains an FPGA and multiple USB ports, which can be configured with Luna to act as a sniffer, proxy, or multi-port device. Proxying: Cynthion's hardware and Luna's software are specifically designed to act as a USB man-in-the-middle, transparently modifying USB data as it flows between the host and device. Bit-banging vs. using a PHY A true bit-banged implementation of a USB host and device stack is very difficult. Most FPGA USB designs use a softcore CPU running a software USB stack. A fully bit-banged solution is susceptible to timing errors, but using a cheap FPGA to implement a host and device stack via a softcore is the correct "down on the wire" approach you're looking for, and Luna is the right tool to use. there existing tooling for a cheaper platform Yes, existing open-source tooling like the Luna framework is compatible with several cheaper FPGAs, including low-cost Gowin and Lattice boards . The key is to implement the USB logic on the FPGA itself, rather than relying on a complex microcontroller or dedicated hub IC. For a DIY USB proxy setup, you would typically need a pair of low-cost FPGA boards. One acts as the USB device (connecting to your computer) and the other as the USB host (connecting to the target peripheral). The Luna framework and the accompanying Amaranth HDL library can be used to develop the gateware for both boards. Building a cheap FPGA USB proxy Hardware Two Sipeed Tang Nano boards: The Sipeed Tang Nano 9K is an excellent choice. At around $20 each, two boards plus a few basic components will cost significantly less than a purpose-built Cynthion. Two USB PHYs: The Tang Nano boards do not have a built-in USB PHY (Physical Layer). You will need to add two separate PHY chips, such as the USB3343, to provide the actual physical connection to the USB bus. The FPGA will handle the higher-level logic. Connecting the boards: Connect the two FPGAs using a high-speed communication channel via their GPIO pins. You could use a standard protocol like SPI or a custom one for maximum throughput. Software Luna framework: This is the core of your software stack. It provides the Amaranth HDL modules needed to implement both the USB host and device gateware. Yosys and nextpnr: These open-source tools will synthesize and place your Amaranth code onto the Gowin FPGAs. This is a crucial part of the open-source FPGA toolchain. Custom Python script: A Python script running on your PC will communicate with the first FPGA (acting as a device). This script can analyze, log, and modify the USB traffic before sending it across to the second FPGA. Bit-banging implementation: Within the Luna framework, you will create the HDL code to bit-bang the USB data. Luna simplifies this process by providing pre-made, reusable modules for handling the USB protocol, making it far easier than writing the entire stack from scratch. Example projects and guidance While a complete, drop-in tool for cheap FPGAs may not exist in the same way as Cynthion's integrated suite, many resources are available from the open-source community to guide you. GitHub repositories: The greatscottgadgets/luna repository and other community projects have examples of Luna gateware designed for various platforms. Project IceStorm: For Lattice FPGAs, the Project IceStorm toolchain is very mature and has numerous examples of low-level USB projects. Forum discussions: The EEVblog and Hackaday.io communities have active discussions and projects detailing USB implementations on low-cost FPGAs. I would like to implement the physical layer. I am happy with usb1 Implementing the USB physical layer "down on the wire" on a cheap FPGA is a significant challenge but a great learning exercise. For USB 1.1, you have two speed options, with different technical demands : Low Speed (LS): 1.5 Mbps. Less susceptible to electrical noise and with less stringent timing requirements. Full Speed (FS): 12 Mbps. Requires more precise timing and can be more difficult to get working reliably. For a physical layer implementation, you will need to pay close attention to the differential signaling and timing requirements. Key concepts for USB 1.1 physical layer Signal lines USB uses a twisted-pair, differential signal called D+ and D-. Data is encoded using a Non-Return-to-Zero Inverted (NRZI) format with bit stuffing to ensure clock synchronization. The signal uses a pair of 3.3V differential voltage levels. For LS, the data lines swing between 0 and 3.3V. Differential signaling Differential signaling is crucial for noise immunity. You cannot simply use GPIOs to drive D+ and D-. The physical layer also requires pull-up and pull-down resistors to signal device presence and speed. For a DIY approach, you can build a simple circuit using standard components to handle the differential signaling. Timing USB 1.1 operates in 1 ms frames. Your FPGA design must handle the precise timing required by the standard. Start-of-Packet (SOP): All packets start with a specific synchronization field, SYNC, followed by the packet ID (PID). End-of-Packet (EOP): A specific sequence signals the end of a packet. Your implementation will need to handle bit stuffing and CRC (Cyclic Redundancy Check) calculation and verification. Recommended approach with cheap FPGAs Hardware Two cheap FPGAs: The Sipeed Tang Nano 9K is still an excellent choice due to its low cost and open-source toolchain support. Breadboard and external components: You will need a breadboard, USB connectors, and passive components for the differential signaling and power delivery. No external PHYs (for USB 1.1 Low Speed): For USB 1.1 Low Speed (1.5 Mbps), it is often possible to omit the external PHY and handle the signaling directly with the FPGA's I/O pins, which is the "down on the wire" approach you're aiming for. This requires careful consideration of the differential voltage levels and termination. For Full Speed (12 Mbps), an external PHY is often more reliable due to tighter timing and impedance requirements. External power supply: Provide a stable 5V and 3.3V power supply to the boards and USB connectors. Gateware (FPGA logic) Bit-banging the D+/D- lines: In your gateware, you will control the D+ and D- pins to generate and receive the USB differential signals. You will need a state machine to manage the different stages of USB communication. Implement the USB stack in logic: Use an HDL (Hardware Description Language) like Verilog or Amaranth to implement the full USB protocol stack, including the physical layer, link layer, and device/host functionality. The Luna framework is an excellent resource for this. Synchronization and clocking: Pay careful attention to clocking. You may need a PLL (Phase-Locked Loop) in the FPGA to generate the precise clock signals required for USB. Proxy logic: A separate module in your gateware would handle the proxying logic. It would intercept packets between the host and device, allowing you to observe or modify the data before re-transmitting it. Software Host software: Use a Python script with the Luna framework to talk to the first FPGA, configure the proxy, and analyze the intercepted data. Verification: Use a USB protocol analyzer or an oscilloscope to verify that your FPGA is correctly generating and receiving USB traffic. Implementation steps Understand the USB 1.1 standard: Read the USB 1.1 specification and familiarize yourself with the protocol, frame structure, and physical layer details. Set up the hardware: Build your breadboard circuit with the two FPGAs, USB connectors, and passive components. Develop the gateware: Write the HDL for the USB physical layer, link layer, and proxy logic. This is the most challenging part of the project. Test and debug: Use test equipment to debug your physical layer implementation and verify that the FPGAs are correctly communicating with each other and with USB devices/hosts. where does this approach fit on existing projects like greatscott? Your "down-on-the-wire" approach using cheap FPGAs to bit-bang the USB physical layer is a ground-up educational project that sits well below the abstraction layers provided by Great Scott Gadgets (GSG), but it is philosophically aligned with their work . Here is how your project fits into the landscape of GSG's work: Philosophical alignment with open hardware and learning The spirit of GSG: GSG's products, including Cynthion and the Luna framework, are founded on the principle of open hardware and making complex protocols like USB accessible for learning and experimentation. Your project, which involves implementing the physical layer yourself, perfectly embodies this spirit of deep, low-level exploration. Democratizing access: GSG's tools aim to replace expensive, proprietary hardware with open-source alternatives. Your project takes this one step further by replacing even the integrated hardware of boards like Cynthion with a completely self-made, low-cost solution, pushing the boundaries of accessibility even further. LUNA - Great Scott Gadgets Feb 15, 2023 — One of LUNA's key features is its ability to act as a passive sniffer: it can be connected between a computer and the USB devices connected to it, capturing all... Great Scott Gadgets Cynthion - Crowd Supply Tools for Reverse Engineering & Security Research As a Great Scott Gadgets (GSG) product Cynthion has been designed from the beginning to enable new and innovat... Crowd Supply Technical differences: Levels of abstraction The primary difference is the level of abstraction at which you are operating. GSG's tools provide a higher-level framework to simplify complex tasks, while your project focuses on the most fundamental level. GSG's Cynthion and Luna: These products abstract away the low-level physical layer. Cynthion hardware and Luna gateware handle the intricate timing and differential signaling of USB 1.1, 2.0, and even SuperSpeed (with a PHY). This allows a user to focus on the protocol logic (packets, transactions, transfers) and the higher-level analysis, proxying, and fuzzing with the Facesdancer framework. Your DIY approach: You are building the equivalent of the physical layer logic that GSG provides in its gateware, but from scratch. Your focus is on the fundamental timing of the SYNC, PID, and data signaling, and managing the state machine for the different stages of communication. This is a very deep dive into the technology. Comparison table Feature Your DIY ProjectGreat Scott Gadgets GoalImplement USB 1.1 physical layer from scratch for maximum low-level control.Provide open-source tools and frameworks (Luna) for USB research, hacking, and development. Abstraction LevelVery low. Focus on bit-banging, timing, and electrical signaling.High. Frameworks handle the physical layer, allowing focus on protocols and applications. HardwareTwo cheap FPGAs (e.g., Tang Nano 9K) and external components for differential signaling.Cynthion, a purpose-built FPGA-based tool with dedicated USB PHYs and integrated logic. ToolingAmaranth/Luna HDL (for logic), Yosys/nextpnr (for synthesis), custom python scripts (for control).Luna gateware (running on Cynthion), Facedancer library (for Python scripting), Packetry (for analysis). OutputLearning experience and a functional USB 1.1 proxy.A mature, polished product ecosystem for advanced USB work. How your work contributes to the ecosystem Even though your project is more of a ground-up effort, it strengthens the same open-source ecosystem that GSG supports. Luna development: By using the Luna framework, you are contributing to its use on low-cost boards, helping to expand its compatibility beyond just the Cynthion platform. Educational resources: Your project can serve as a valuable resource for others who want to learn USB from the ground up, providing a simpler, more approachable alternative to the highly-optimized and integrated GSG products. I mean — if I write new open source code or designs, what open source efforts am I duplicating? While you are not likely to duplicate a full-featured, low-cost FPGA-based USB proxy that implements the physical layer from scratch, you will likely encounter and build upon several existing projects. The open-source community has explored different components of your vision, but not the complete solution you are proposing . Your effort would primarily be combining existing tools and techniques in a novel way for a specific purpose. Here is a breakdown of the existing open-source work and how your project would build upon it: USB protocol stack and proxying logic (Luna) What exists: The Luna framework, developed by Great Scott Gadgets, provides a robust, reusable set of modules written in Amaranth HDL for implementing various parts of the USB stack. Host and device logic: Luna includes gateware for implementing both USB device and host roles. Proxy and analysis: When used with the Cynthion hardware, Luna allows for transparent USB proxying and protocol analysis. PHY abstraction: Luna handles the higher-level logic and abstracts the physical layer, assuming a PHY is present. Your project's contribution: You would take the Luna host and device modules and adapt them to work with your custom, bit-banged physical layer, rather than a dedicated PHY chip. You would also create the gateware to link the host and device Luna stacks to create the proxy functionality. Bit-banged USB physical layer What exists: The concept of bit-banging the USB physical layer is not new, particularly for USB 1.1 Low Speed, and has been implemented on microcontrollers. Some FPGA developers have also successfully achieved this, but usually as an isolated proof-of-concept. Your project's contribution: You would likely be developing a new, self-contained, and open-source USB 1.1 physical layer implementation in Amaranth or Verilog that can integrate directly with the Luna framework. While similar projects may exist in Verilog, an Amaranth implementation is less common for this specific task. Cheap FPGA hardware and tooling What exists: There is excellent open-source support for inexpensive FPGA boards, especially the Sipeed Tang Nano series (using the Gowin toolchain) and the TinyFPGA boards (using the Project IceStorm toolchain). Toolchains: Open-source toolchains like Yosys, nextpnr, and Amaranth provide a complete software stack for developing and synthesizing gateware for these boards. Board support: Many community projects have created board definitions and example projects for these low-cost FPGAs. Your project's contribution: Your work would primarily involve creating the glue logic and pin definitions to connect Luna's USB stack to the specific I/O pins of your chosen cheap FPGA boards, along with any external components for the physical layer. System integration (Proxy) What exists: While Cynthion provides a full, integrated hardware and software solution for USB proxying, no such equivalent exists for a low-cost, multi-FPGA setup with a bit-banged physical layer. Your project's contribution: You would be pioneering this specific, ground-up approach. Your most significant contribution would be the complete design, from the physical layer to the application-level proxy logic, all integrated and tested on cheap, accessible hardware. In summary, your effort is an original combination of existing parts. You would not be duplicating existing work but rather bridging a gap by integrating an open-source USB framework (Luna) with a low-cost, self-implemented physical layer on cheap FPGA hardware, something that, as a complete project, does not currently exist. sorry — can you briefly tell me what existing projects do not require phy chips? any with fpga? While implementing USB communication on an FPGA without a separate physical layer (PHY) chip is a well-understood and difficult task, there are existing open-source projects that accomplish this. These projects generally focus on USB 1.1 Low or Full Speed and are considered advanced because they require detailed knowledge of the USB standard. The most notable open-source project that works without a PHY chip is Fomu, which implements a USB device stack entirely within the fabric of an iCE40 FPGA. Fomu (Lattice iCE40) The Fomu is a tiny FPGA board that fits directly into a USB port. Its design demonstrates how to handle USB signaling directly with the FPGA fabric, leveraging the open-source toolchains for Lattice iCE40 devices. Gateware: Fomu uses the ValentyUSB core, an open-source USB gateware library. Protocol Support: It implements a USB 1.1 Full Speed device, allowing it to emulate various USB devices. Tooling: Fomu uses a fully open-source toolchain, including Yosys, nextpnr, and Project IceStorm, to build its gateware. ValentyUSB The ValentyUSB gateware library is the key component behind the Fomu's USB capabilities. Purpose: ValentyUSB was created to provide a complete, open-source USB core for FPGAs. It handles the low-level physical layer signaling, including timing, NRZI encoding/decoding, bit stuffing, and CRC calculation. Availability: While originally developed for the Fomu, ValentyUSB is a reusable IP core that can theoretically be integrated into any FPGA design, provided the target FPGA has the resources and can meet the timing requirements. TinyFPGA Bootloader The TinyFPGA project, which predates the Fomu, also has an open-source USB bootloader that runs directly on the FPGA without an external chip. Function: It implements a USB virtual serial port to flash the FPGA's configuration memory. Mechanism: It works by bit-banging the USB signals directly from the FPGA's general-purpose I/O pins. This is primarily for device configuration, not for full-featured USB communication. Key considerations Timing: The biggest challenge for any no-PHY solution is meeting the precise timing requirements of the USB specification. Fomu's success relies on the specific characteristics of the iCE40 FPGA fabric. Full vs. Low Speed: Implementing Low Speed USB (1.5 Mbps) is significantly easier than Full Speed (12 Mbps), as the timing margins are more forgiving. Fomu implemented Full Speed, which was a major achievement. Host vs. Device: Implementing a USB Host without a PHY is considerably more difficult than a USB device. The host must manage power, handle enumeration, and deal with more complex timing and error handling. For this reason, most no-PHY projects focus on the device role. does the nano 9k meet the timing requirements It is uncertain if the Tang Nano 9K can meet the timing requirements for a purely bit-banged USB 1.1 Full Speed (12 Mbps) implementation, though it's much more feasible for Low Speed (1.5 Mbps) . While some FPGA boards are capable of this, relying on an external PHY for Full Speed is generally recommended for stability, even in hobbyist projects. Bit-banged USB on FPGAs Feasibility: Bit-banging USB 1.1 Full Speed on an FPGA without a dedicated PHY is an extremely difficult endeavor. It demands precise timing control over the I/O pins, and reliability is heavily dependent on the specific board and chip characteristics, including trace lengths, impedance, and the FPGA fabric itself. Lattice iCE40 success: The success of the Fomu, which uses a Lattice iCE40 FPGA, is a testament to the specific capabilities of that chip family and the careful engineering of the ValentyUSB gateware. It is not guaranteed that a similar implementation on a different FPGA family would work as reliably. Gowin's approach: Gowin Semiconductor, the manufacturer of the Tang Nano 9K's GW1NR-9 FPGA, provides its own soft IP core for USB 1.1 that supports both Low and Full Speed modes. This IP core is designed to work within Gowin's EDA software and is the vendor-supported method for implementing USB on their FPGAs. While it does implement a "soft PHY" in logic, it is still intended to be used with specific external circuitry, and its reliability can depend on the speed grade of the chip. Challenges for the Tang Nano 9K No proven open-source implementation: The open-source community has not demonstrated a robust, entirely bit-banged Full Speed USB stack for the GW1NR-9 FPGA. While the Luna framework is hardware-agnostic, adapting a PHY-less stack from a different FPGA family requires significant work and verification. Onboard circuitry: The Tang Nano 9K includes an onboard BL702 chip that acts as a USB-JTAG and USB-UART bridge. This adds complexity and potential noise, which could further complicate a sensitive, bit-banged USB implementation. Timing analysis: Creating a bit-banged USB stack for Full Speed requires meticulous timing analysis and synthesis constraints to ensure the FPGA logic can meet the strict timing requirements of the protocol. Without prior community success, this is a research-level effort. Conclusion For the lowest-speed, most "down-on-the-wire" project, USB 1.1 Low Speed (1.5 Mbps) is the most feasible target for a bit-banged implementation on the Tang Nano 9K, though it would still require significant effort. A bit-banged Full Speed (12 Mbps) implementation is highly challenging and speculative on this platform. For a Full Speed project, using Gowin's Soft PHY IP core or adding an external PHY would be a more reliable path. it sounds like the fomu is the cheapest product you know about that has active community work and support and such. since timing sounds important I may want to get a logic analyzer or oscilloscope. is there anything cheap with active transparent work? For an affordable logic analyzer with active, transparent development, the best option is a cheap Saleae clone used with the Sigrok software suite. This combination is widely recognized and used by hobbyists for its low cost and open-source software, making it a "no-brainer" entry point into signal analysis. Cheap Saleae clones Hardware: These are unbranded, inexpensive hardware devices, typically with 8 channels and a 24 MHz sample rate. They are available from online retailers like AliExpress and often cost under $20. Performance: While they lack the high-end features and performance of genuine Saleae products, they are perfectly sufficient for debugging slower protocols like Low-Speed USB, I2C, and SPI. Sigrok software suite PulseView: The primary graphical front-end for Sigrok. It provides a clean interface for visualizing digital signals, decoding protocols, and analyzing captures. Open-source and cross-platform: Sigrok is a portable, cross-platform software suite with transparent, open-source development, aligning perfectly with your criteria. Protocol decoders: The software supports a wide range of protocol decoders, allowing you to automatically decode signals from standard buses and even custom protocols, which can be invaluable for understanding the low-level USB bit-banging. Other budget options Oscilloscope DIY options: If you need to visualize the analog waveforms of your USB signals, some projects exist that use microcontrollers or repurposed hardware (like USB sound cards) to create a basic oscilloscope. However, these typically offer low bandwidth and are mainly for educational purposes. Used benchtop scopes: A more capable, but more expensive option is a used analog oscilloscope, which can be found for relatively low prices on sites like eBay. Mixed-signal oscilloscopes (MSOs) High-end solution: MSOs combine the functionality of an oscilloscope and a logic analyzer. They are expensive but provide the best of both worlds, allowing you to view both the analog waveform and the digital timing of your signals simultaneously. For your specific project focusing on the USB physical layer, a cheap logic analyzer with Sigrok is the most cost-effective and transparent solution. An oscilloscope would also be beneficial to observe the analog differential signals (D+ and D-), but a logic analyzer is essential for decoding the digital protocol. are the fomu, ch32v003, or rp2040 used as a scope or analyzer ever? I’m also looking at classic chips like the 6052 or z80; does anybody use these for tooling? Yes, both the RP2040 and Fomu have been used to create open-source logic analyzers . The CH32V003 has also seen some use, though it is less common due to its hardware limitations. Older chips like the 6502 and Z80 are not practical for this kind of high-speed tooling. Modern microcontrollers and FPGAs RP2040 ( Raspberry Pi Pico ) The RP2040 is a very popular choice for DIY logic analyzers because of its flexible Programmable I/O (PIO) state machine hardware. μLA: The dotcypress/ula project on GitHub provides open-source firmware that turns an RP2040 board, such as the Raspberry Pi Pico, into a 16-channel, 100 MHz logic analyzer. Sigrok integration: This and other RP2040 logic analyzer projects are compatible with the Sigrok software suite, meaning you can use the open-source PulseView GUI to visualize and decode captured signals. 24-channel variant: Another project on GitHub, gusmanb/logicanalyzer, offers a 24-channel version with a 100 Msps sample rate. Raspberry Pi Pico 2 $4.99 4.8(358) Olimex LTD RP2040-PICO-W-HDR RASPBERRY PI PICO WH RP2040 $11.72 Fomu (Lattice iCE40 FPGA) Because the Fomu is an FPGA, it is inherently reconfigurable, making it a very flexible platform for building custom tools. FPGA logic analyzer: The core concept of "building a logic analyzer into an FPGA" is common for debugging projects on that same FPGA. You can also design gateware to turn the Fomu itself into a self-contained analyzer. ValentyUSB integration: With the ValentyUSB core that the Fomu already uses, you could develop a project that uses one Fomu as an analyzer and the other as the target of your USB bit-banging efforts. CH32V003 (RISC-V MCU) The CH32V003 is less common for logic analyzers because its hardware lacks the high-speed capture capabilities of the RP2040's PIO or the flexibility of an FPGA. Low sample rates: A CH32V003-based logic analyzer would be limited to significantly lower sample rates and fewer channels. This makes it unsuitable for analyzing high-speed protocols like Full Speed USB. Experimental use: It has likely been used in hobbyist projects to capture very slow signals, but no prominent, actively developed open-source analyzer projects exist for it that can compete with RP2040- or FPGA-based tools. Classic chips (6502/Z80) Classic microprocessors like the 6502 and Z80 are unsuitable for modern signal analysis tools. Slow clock speeds: Their 1–8 MHz clock speeds are far too slow to capture and analyze signals from a 12 Mbps USB connection or other modern buses. Limited hardware: They lack the necessary hardware for high-speed input capture, data buffering, and USB communication. Vintage debugging: When debugging vintage systems, modern microcontrollers (like the RP2040) are often used to build debugging tools. One example is using a Teensy to build a logic analyzer to trace a 6502's signals. This confirms that a modern, fast processor is necessary to analyze the older chips.
