Corinna Vinschen writes: > Btw., can you please also check /proc/cpuinfo?
The output is correct now for a SandyBridge dual-core CPU with logical processors (aka HT) and an IvyBridge dual-core CPU w/o HT. I've also tried to find out why the L3 cache is not reported for AMD in cpuinfo. It seems the reason is that it is logically part of the northbridge system, even if it is on-die and gets reported via CPUID. Regards, Achim. -- +<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+ SD adaptation for Waldorf microQ V2.22R2: http://Synth.Stromeko.net/Downloads.html#WaldorfSDada -- Problem reports: http://cygwin.com/problems.html FAQ: http://cygwin.com/faq/ Documentation: http://cygwin.com/docs.html Unsubscribe info: http://cygwin.com/ml/#unsubscribe-simple
