On Tue, Jan 19, 2021 at 9:27 AM Michał Żygowski <michal.zygow...@3mdeb.com> wrote:
> > On 1/19/21 5:10 PM, Tim Wawrzynczak via coreboot wrote: > > Dear Michał, > > > > Do you have a config for us to look at for your board? Are you > > using INTEL_CAR_NEM_ENHANCED ? > > Hi Tim, > > Sure, see attached, yes INTEL_CAR_NEM_ENHANCED is selected. > > > > Based on the post code you observed last, I might guess that you > > overfilled the cache when doing the cache fill > > operation, e.g. the next few lines in cache_as_ram.S after post-code > > 0x26; doing so will cause a MCE. > > Do you know how much data you're trying to place in the cache > > (CONFIG_DCACHE_RAM_SIZE) and also how much LLC your SKU has? > Not sure about LLC size, but yeah, caching whole SPI (32MB) may be too > big. Maybe this is the problem. This is a Super SKU. > CONFIG_DCACHE_RAM_SIZE=0x80000 > That would absolutely be a problem :) The biggest LLC we've seen on the UP3 parts is 12MB, IIRC, starting as low as ~4MB, IIRC. The goal of eNEM is to keep all of the modifiable data (e.g. stack) in cache ways that are marked as 'no-evict', but also to keep code in cache when feasible; however the code is kept in cache ways that are marked as evictable, because in CAR, obviously the code comes from SPI flash, so it is OK to flush out those cache lines because the data has a backing store. To make this scheme work, you need to ensure that you are not using more than (LLC Size - 0.5 MiB) of the LLC during CAR, or you will (probably) get a MCE, and hang with just a few post codes to debug with :) -Tim > > FYI, Tiger Lake has some new requirements for CAR setup when using > > eNEM mode, which > > should be taken care of by the default soc/intel/tigerlake/Kconfig > > file. Do you have local changes to that? > No changes except the FMD layout to give more space for > COREBOOT/FW_MAIN_A/FW_MAIN_B by sacrificing RW_LEGACY. > > > > You can also see mb/google/volteer for an example of a functional TGL > > coreboot board, feel free to ask me > > any other questions you have. > Will visit it and check it. > > > > Cheers, > > - Tim > Regards, > > -- > Michał Żygowski > Firmware Engineer > https://3mdeb.com | @3mdeb_com > > > > > > > On Tue, Jan 19, 2021 at 8:58 AM Michał Żygowski > > <michal.zygow...@3mdeb.com <mailto:michal.zygow...@3mdeb.com>> wrote: > > > > Dear coreboot community, > > > > I have a Tiger Lake UP3 RVP and I try to build a working coreboot > > on it, > > however facing an early stuck during CAR setup. Tried different > > approaches: > > > > - native coreboot's CAR setup - the last seen post code is 0x26 > > - FSP-T CAR setup - the last seen post code is 0x7F (which is > > TempRamInit Exit event according to FSP integration guide), FSP from > > public repo, Client variant > > > > Used microcode from original RVP firmware. > > > > Are there any patches that I have to apply to make it working? > > > > Best regards, > > > > -- > > Michał Żygowski > > Firmware Engineer > > https://3mdeb.com <https://3mdeb.com> | @3mdeb_com > > _______________________________________________ > > coreboot mailing list -- coreboot@coreboot.org > > <mailto:coreboot@coreboot.org> > > To unsubscribe send an email to coreboot-le...@coreboot.org > > <mailto:coreboot-le...@coreboot.org> > > > > > > _______________________________________________ > > coreboot mailing list -- coreboot@coreboot.org > > To unsubscribe send an email to coreboot-le...@coreboot.org > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org >
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