Dear Michał, Do you have a config for us to look at for your board? Are you using INTEL_CAR_NEM_ENHANCED ?
Based on the post code you observed last, I might guess that you overfilled the cache when doing the cache fill operation, e.g. the next few lines in cache_as_ram.S after post-code 0x26; doing so will cause a MCE. Do you know how much data you're trying to place in the cache (CONFIG_DCACHE_RAM_SIZE) and also how much LLC your SKU has? FYI, Tiger Lake has some new requirements for CAR setup when using eNEM mode, which should be taken care of by the default soc/intel/tigerlake/Kconfig file. Do you have local changes to that? You can also see mb/google/volteer for an example of a functional TGL coreboot board, feel free to ask me any other questions you have. Cheers, - Tim On Tue, Jan 19, 2021 at 8:58 AM Michał Żygowski <michal.zygow...@3mdeb.com> wrote: > Dear coreboot community, > > I have a Tiger Lake UP3 RVP and I try to build a working coreboot on it, > however facing an early stuck during CAR setup. Tried different approaches: > > - native coreboot's CAR setup - the last seen post code is 0x26 > - FSP-T CAR setup - the last seen post code is 0x7F (which is > TempRamInit Exit event according to FSP integration guide), FSP from > public repo, Client variant > > Used microcode from original RVP firmware. > > Are there any patches that I have to apply to make it working? > > Best regards, > > -- > Michał Żygowski > Firmware Engineer > https://3mdeb.com | @3mdeb_com > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org >
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