Carl-Daniel Hailfinger wrote: > >>> Unsure. You would then be powering one of the 3v3 rails (where the > >>> flash chip is connected) from the programmer, without powering any > >>> other rail on the board. The southbridge may not like it at all > >>> when your programmer drives the SPI pins in that state. > >> Hmmm, I wonder what the potential for permanent damage is? > > I also don't know. It depends on what the IO drivers are like in the > > southbridge. > > I wouldn't fear permanent damage on the mainboard,
Don't be so sure. If the power rail sequencing is wrong - and I do not know if the 3v3 rail that the flash chip connects to is the first one that must come up - there can be real trouble. //Peter -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
