Graeme Russ wrote: > > Unsure. You would then be powering one of the 3v3 rails (where the > > flash chip is connected) from the programmer, without powering any > > other rail on the board. The southbridge may not like it at all > > when your programmer drives the SPI pins in that state. > > Hmmm, I wonder what the potential for permanent damage is?
I also don't know. It depends on what the IO drivers are like in the southbridge. > So to be safe: > - Jumper the front panel reset pins > - Power-on the motherboard > - Do a current test from VCC to each of the CS#, HOLD#, WP#, SCLK, > SI, and SO pins To be really safe test both from VCC to pin, as well as from pin to GND. HOLD# and WP# are never really used, and you don't even have to connect them to the programmer. > - Connect the programmer without connecting the programmers VCC > - Program the chip Yep, that's it. //Peter -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
