I am not sure. I think we need to leave the workload to compiler, instead of to the machine running the coreboot and to the people.
Zheng > -----Original Message----- > From: [email protected] [mailto:[email protected]] > On Behalf Of Patrick Georgi > Sent: Friday, December 10, 2010 8:10 PM > To: [email protected] > Subject: Re: [coreboot] [PATCH] Set the register based on the ROMSIZE > > Am 10.12.2010 13:02, schrieb Bao, Zheng: > > Set the register based on the ROMSIZE. > > > @@ -57,8 +57,18 @@ > > * Enable LPC ROM range start at: > > * 0xfff8(0000): 512KB > > * 0xfff0(0000): 1MB > > + * 0xffe0(0000): 2MB > > + * 0xffc0(0000): 4MB > > */ > > + #if CONFIG_COREBOOT_ROMSIZE_KB_512 || > > CONFIG_COREBOOT_ROMSIZE_KB_256 || CONFIG_COREBOOT_ROMSIZE_KB_128 > > + pci_write_config16(dev, 0x6c, 0xfff8); /* 512KB */ > > + #elif CONFIG_COREBOOT_ROMSIZE_KB_1024 > > pci_write_config16(dev, 0x6c, 0xfff0); /* 1 MB */ > > + #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 > > + pci_write_config16(dev, 0x6c, 0xffe0); /* 2 MB */ > > + #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 > > + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ > > + #endif > How about > pci_write_config16(dev, 0x6c, > 0x10000-(max(512,CONFIG_COREBOOT_ROMSIZE_KB)>>6)); > instead? > > > Patrick > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
