On Sun, Aug 10, 2008 at 5:30 PM, Carl-Daniel Hailfinger
<[EMAIL PROTECTED]> wrote:
> On 11.08.2008 02:18, ron minnich wrote:
>> the k8 north makefile and raminit.c are committed rev 736.
>>
>> Current status:
>> Index: southbridge/nvidia/mcp55/mcp55_smbus.h
>>
>
> I believe that one was never posted.
attached.
New arch/x86/Kconfig attached. I responded to all the comments save this one:
> +
> +config K8_SCAN_PCI_BUS
> + hex
> + default 0 if CPU_AMD_K8
> + help
> + Whether to scan the PCI bus on startup
>
>Since when do we not scan the PCI bus by default?
> +
> +config K8_ALLOCATE_IO_RANGE
> + hex
> + default 0 if CPU_AMD_K8
> + help
> + Whether to allocate IO space on startup
>
>Same question here.
Stage 1 again. Let's keep in mind, the rules in stage1 vary by
mainboard for good reasons in most cases. I don't want to get into
this at this time, this code has been this way for years on v2.
thanks
ron
Move code to a .c file -- now there's an idea!
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: southbridge/nvidia/mcp55/mcp55_smbus.h
===================================================================
--- southbridge/nvidia/mcp55/mcp55_smbus.h (revision 730)
+++ southbridge/nvidia/mcp55/mcp55_smbus.h (working copy)
@@ -41,157 +41,3 @@
(void) inb(0x80);
}
-static int smbus_wait_until_ready(u16 smbus_io_base)
-{
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- do {
- unsigned char val;
- smbus_delay();
- val = inb(smbus_io_base + SMBHSTSTAT);
- val &= 0x1f;
- if (val == 0) {
- return 0;
- }
- outb(val,smbus_io_base + SMBHSTSTAT);
- } while(--loops);
- return -2;
-}
-
-static int smbus_wait_until_done(u16 smbus_io_base)
-{
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- do {
- unsigned char val;
- smbus_delay();
-
- val = inb(smbus_io_base + SMBHSTSTAT);
- if ( (val & 0xff) != 0) {
- return 0;
- }
- } while(--loops);
- return -3;
-}
-
-static int do_smbus_recv_byte(u16 smbus_io_base, u8 device)
-{
- u8 global_status_register;
- u8 byte;
-
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
- smbus_delay();
-
- /* byte data recv */
- outb(0x05, smbus_io_base + SMBHSTPRTCL);
- smbus_delay();
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3;
- }
-
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
-
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTCMD);
-
- if (global_status_register != 0x80) { // loose check, otherwise it should be 0
- return -1;
- }
- return byte;
-}
-
-static int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val)
-{
- u8 global_status_register;
-
- outb(val, smbus_io_base + SMBHSTDAT0);
- smbus_delay();
-
- /* set the command... */
- outb(val, smbus_io_base + SMBHSTCMD);
- smbus_delay();
-
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
- smbus_delay();
-
- /* set up for a byte data write */
- outb(0x04, smbus_io_base + SMBHSTPRTCL);
- smbus_delay();
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3;
- }
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
-
- if (global_status_register != 0x80) {
- return -1;
- }
- return 0;
-}
-
-static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
-{
- u8 global_status_register;
- u8 byte;
-
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD);
- smbus_delay();
- /* set the command/address... */
- outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- smbus_delay();
- /* byte data read */
- outb(0x07, smbus_io_base + SMBHSTPRTCL);
- smbus_delay();
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3;
- }
-
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */
-
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTDAT0);
-
- if (global_status_register != 0x80) { // lose check, otherwise it should be 0
- return -1;
- }
- return byte;
-}
-
-static int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val)
-{
- u8 global_status_register;
-
- outb(val, smbus_io_base + SMBHSTDAT0);
- smbus_delay();
-
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD);
- smbus_delay();
-
- outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- smbus_delay();
-
- /* set up for a byte data write */
- outb(0x06, smbus_io_base + SMBHSTPRTCL);
- smbus_delay();
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3;
- }
- global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */;
-
- if (global_status_register != 0x80) {
- return -1;
- }
- return 0;
-}
-
New config variables for K8.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: arch/x86/Kconfig
===================================================================
--- arch/x86/Kconfig (revision 736)
+++ arch/x86/Kconfig (working copy)
@@ -56,6 +56,58 @@
arch/x86/Makefile for more hints on possible values.
It is usually set in mainboard/*/Kconfig.
+config K8_REV_F_SUPPORT
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Whether to include rev F support
+
+config K8_SCAN_PCI_BUS
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Whether to scan the PCI bus in stage1
+
+config K8_ALLOCATE_IO_RANGE
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Whether to allocate IO space in stage1
+
+config K8_ALLOCATE_MMIO_RANGE
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Whether to allocate MMIO space in stage1.
+ Comment from code:
+ Do we need allocate MMIO? Currently we direct
+ last 64M to southbridge link (sblink) only,
+ We can not lose access to last 4M range to ROM.
+
+config LOGICAL_CPUS
+ hex
+ default 1
+ help
+ How many logical CPUs there are. Fix me.
+
+config MAX_PHYSICAL_CPUS
+ hex
+ default 1
+ help
+ Max number of physical CPUs (sockets)
+
+config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Config with 4 CPUs even if more are installed
+
+config CROSS_BAR_47_56
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Configure for the type of crossbar on the mainboard.
+
config OPTION_TABLE
boolean
help
@@ -93,3 +145,50 @@
default 0x8000 if CPU_AMD_K8
help
This option sets the size of the area used for CAR.
+
+# variables related to AMD Hypertransport.
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Hypertransport unit ID base value.
+ Mainboard-dependent.
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x20 if CPU_AMD_K8
+ help
+ Unit id of the end of hypertransport chain
+ (usually the real SB); if it is
+ less than than HT_CHAIN_UNITID_BASE,
+ it can be 0
+
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ hex
+ default 1 if CPU_AMD_K8
+ help
+ Determines (I don't understand; ask YHLU)
+ if only offset SB hypertransport chain
+
+config SB_HT_CHAIN_ON_BUS0
+ hex
+ default 0 if CPU_AMD_K8
+ help
+ Make SB hypertransport chain sit on bus 0, if it is 1,
+ will put sb ht chain on bus 0, if it is 2 will
+ put other chain on 0x40, 0x80, 0xc0
+
+
+config K8_HT_FREQ_1G_SUPPORT
+ hex
+ default 1 if CPU_AMD_K8
+ help
+ 1 Ghz. support. Opteron E0 or later can support
+ 1G HT, but still depends on the mainboard
+
+config HT_FREQ_800MHZ
+ hex
+ default 1 if CPU_AMD_K8
+ help
+ Can we run HT at 800 Mhz
+
--
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