mainboard patched.
ron
Add more support so mainboard and other bits build correctly.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: mainboard/gigabyte/m57sli/initram.c
===================================================================
--- mainboard/gigabyte/m57sli/initram.c (revision 730)
+++ mainboard/gigabyte/m57sli/initram.c (working copy)
@@ -29,6 +29,7 @@
#include <string.h>
#include <msr.h>
#include <io.h>
+#include <cpu.h>
#include <amd/k8/k8.h>
#include <spd.h>
Index: mainboard/gigabyte/m57sli/stage1.c
===================================================================
--- mainboard/gigabyte/m57sli/stage1.c (revision 730)
+++ mainboard/gigabyte/m57sli/stage1.c (working copy)
@@ -23,12 +23,29 @@
#include <lib.h>
#include <console.h>
#include <device/device.h>
+#include <cpu.h>
+#include <amd/k8/k8.h>
+#include <amd/k8/sysconf.h>
#include <device/pci.h>
#include <string.h>
#include <msr.h>
#include <io.h>
#include <arch/x86/msr.h>
+void memreset_setup(void)
+{
+}
+
+void memreset(int controllers, const struct mem_controller *ctrl)
+{
+}
+
+void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+
+
void hardware_stage1(void)
{
post_code(POST_START_OF_MAIN);
Index: mainboard/gigabyte/m57sli/Makefile
===================================================================
--- mainboard/gigabyte/m57sli/Makefile (revision 730)
+++ mainboard/gigabyte/m57sli/Makefile (working copy)
@@ -21,10 +21,12 @@
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \
$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c \
- $(obj)/southbridge/nvidia/mcp55/stage1_smbus.o
+ $(obj)/southbridge/nvidia/mcp55/stage1_smbus.o \
+ $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \
+ $(obj)/northbridge/amd/k8/raminit.o \
+ $(obj)/northbridge/amd/k8/coherent_ht.o \
+ $(obj)/northbridge/amd/k8/incoherent_ht.o
-INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
-
STAGE2_MAINBOARD_SRC =
$(obj)/coreboot.vpd:
--
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