On Wed, 17 Jun 2026 11:53:57 GMT, Andrew Dinn <[email protected]> wrote:
>> This idea sounds great, but, unfortunately, in st2(v1, v2, T, post(base, >> 32)) it is required that the register index of v2 be one more than that of >> v1, so I just added a comment at the consuming part. > > Ah, yes. That's a shame as saving the data in canonical order would be much > better. We could salvage this by redeclaring the sequences so that adjacent > elements A[i] and D[i] are adjacent vector registers. > > VSeq<4> A(16, 2); > VSeq<4> D(17, 2); > VSeq<4> B(24); > VSeq<4> C(28); > > or equivalently > > VSeq<8> A_D(16); > VSeq<4> A = vs_even(A_D); > VSeq<4> D = vs_odd(A_D); > VSeq<4> B(24); > VSeq<4> C(28); > > but then a reader needs to work out why this is being done. > > I'll settle for your comment that restates the permuted layout just prior to > the ldrs. I was also considering the above, but thought that the comment was the more readable solution. ------------- PR Review Comment: https://git.openjdk.org/jdk/pull/30941#discussion_r3430753417
