On Tue, 28 Jun 2022 12:42:57 GMT, Quan Anh Mai <d...@openjdk.org> wrote:
>> src/hotspot/cpu/x86/x86_64.ad line 13043: >> >>> 13041: __ cmpl($src1$$Register, $src2$$Register); >>> 13042: __ movl($dst$$Register, -1); >>> 13043: __ jccb(Assembler::below, done); >> >> By placing compare adjacent to conditional jump in-order frontend can >> trigger macro-fusion. >> Kindly refer section 3.4.2.2 of Intel's optimization manual. > > I realised that by swapping the `mov` and the `cmp` instruction, the rule > needs to have `dst` different from `src1` and `src2`, which increases > register pressure. I do not follow your comment, allocation decisions purely based on LRGs interferences and data flow attributes attached to operands and is agnostic to encoding block contents. ------------- PR: https://git.openjdk.org/jdk/pull/9068
