davids5 commented on PR #6287:
URL: https://github.com/apache/incubator-nuttx/pull/6287#issuecomment-1129916671
@slorquet I have pinged Jukka on Slack, I looking at this in detail now: I
just has a quick look at the Clock tree and the code more carefully. Thing make
less sense now :(
The HSI is the default clock on reset:
The original code
```
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_HSEON | RCC_CR_HSI48ON |
RCC_CR_CSION | RCC_CR_PLL1ON |
RCC_CR_PLL2ON | RCC_CR_PLL3ON |
RCC_CR_HSIDIV_MASK);
/* Set HSI predivider to default (4, 16MHz) */
regval |= RCC_CR_HSIDIV_4;
```
So this code is :
RCC_CR_HSIDIV_MASK is dropping the default.
and the regval |= RCC_CR_HSIDIV_4; is adding it back
So the comments say....But the RM0433 Rev 7 says:
```
Bits 4:3 HSIDIV[1:0]: HSI clock divider
Set and reset by software.
These bits allow selecting a division ratio in order to configure the wanted
HSI clock frequency. The
HSIDIV cannot be changed if the HSI is selected as reference clock for at
least one enabled PLL
(PLLxON bit set to ‘1’). In that case, the new HSIDIV value is ignored.
00: Division by 1, hsi(_ker)_ck = 64 MHz (default after reset)
01: Division by 2, hsi(_ker)_ck = 32 MHz
10: Division by 4, hsi(_ker)_ck = 16 MHz
11: Division by 8, hsi(_ker)_ck = 8 MHz
```
So it is really slowing down the system by 4X at boot.
I wonder if the HW he was debugging was an issue. Let's see what he says.
My take is: It s it better to boot faster and make it work with 00:
Division by 1, hsi(_ker)_ck = 64 MHz (default after reset), then set up the
clock tree and the the final setting can be done with the divisor once the
clock tree is configured.
Which is the direction you have taken. I know you ran it as a test, but did
you review and verify the code path's order of operations of modifying the
clock tree without the drop and ensure there is not an issue with going out of
spec on the PLL set up?
Are you up for that? If not the safe thing to do is leave the original code
with the /4 and your final change.
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