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commit 6fa4a42e34191e559ed5849511da0e6be63490bd
Author: Abdelatif Guettouche <abdelatif.guettou...@espressif.com>
AuthorDate: Sat Mar 12 23:38:01 2022 +0100
xtensa/: Save A3 as part of the regular context saving.
It was separate because the syscal handler was using it before calling
_xtensa_context_save. The order of operations has now changed and we
can save A3 with the rest of the context.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettou...@espressif.com>
---
arch/xtensa/src/common/xtensa_context.S | 2 +
arch/xtensa/src/common/xtensa_int_handlers.S | 88 +++++++++++++---------------
arch/xtensa/src/common/xtensa_panic.S | 1 -
arch/xtensa/src/common/xtensa_user_handler.S | 18 +++---
4 files changed, 50 insertions(+), 59 deletions(-)
diff --git a/arch/xtensa/src/common/xtensa_context.S
b/arch/xtensa/src/common/xtensa_context.S
index 2d2d9d9..ec78a44 100644
--- a/arch/xtensa/src/common/xtensa_context.S
+++ b/arch/xtensa/src/common/xtensa_context.S
@@ -115,6 +115,7 @@
_xtensa_context_save:
+ s32i a3, sp, (4 * REG_A3)
s32i a4, sp, (4 * REG_A4)
s32i a5, sp, (4 * REG_A5)
s32i a6, sp, (4 * REG_A6)
@@ -307,6 +308,7 @@ _xtensa_context_restore:
l32i a3, a2, (4 * REG_SAR)
wsr a3, SAR
+
l32i a3, a2, (4 * REG_A3)
l32i a4, a2, (4 * REG_A4)
l32i a5, a2, (4 * REG_A5)
diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S
b/arch/xtensa/src/common/xtensa_int_handlers.S
index e2b71dd..48ce9c7 100644
--- a/arch/xtensa/src/common/xtensa_int_handlers.S
+++ b/arch/xtensa/src/common/xtensa_int_handlers.S
@@ -303,6 +303,7 @@ _xtensa_level1_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_1
/* Save interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
#ifdef CONFIG_XTENSA_INTBACKTRACE
wsr sp, EXCSAVE_1
@@ -310,9 +311,7 @@ _xtensa_level1_handler:
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
- call0 _xtensa_context_save /* Save full register
state */
+ call0 _xtensa_context_save
/* Save current SP before (possibly) overwriting it, it's the register save
* area. This value will be used later by dispatch_c_isr to retrieve the
@@ -347,13 +346,13 @@ _xtensa_level1_handler:
/* Restore only level-specific regs (the rest were already restored) */
- l32i a0, a2, (4 * REG_PS) /* Retrieve
interruptee's PS */
+ l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */
wsr a0, PS
- l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
+ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
wsr a0, EPC_1
- l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
rsync
/* Ensure PS and EPC written */
/* Return from exception. RFE returns from either the
UserExceptionVector
@@ -406,6 +405,7 @@ _xtensa_level2_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_2 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
#ifdef CONFIG_XTENSA_INTBACKTRACE
wsr sp, EXCSAVE_2
@@ -413,9 +413,7 @@ _xtensa_level2_handler:
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
- call0 _xtensa_context_save /* Save full register
state */
+ call0 _xtensa_context_save
/* Save current SP before (possibly) overwriting it, it's the register
save
* area. This value will be used later by dispatch_c_isr to retrieve the
@@ -450,13 +448,13 @@ _xtensa_level2_handler:
/* Restore only level-specific regs (the rest were already restored) */
- l32i a0, a2, (4 * REG_PS) /* Retrieve
interruptee's PS */
+ l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */
wsr a0, EPS_2
- l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
+ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
wsr a0, EPC_2
- l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Remove interrupt
stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
rsync
/* Ensure EPS and EPC written */
/* Return from interrupt. RFI restores the PS from EPS_2 and jumps to
@@ -484,6 +482,7 @@ _xtensa_level3_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_3 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
#ifdef CONFIG_XTENSA_INTBACKTRACE
wsr sp, EXCSAVE_3
@@ -491,9 +490,7 @@ _xtensa_level3_handler:
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
- call0 _xtensa_context_save /* Save full register
state */
+ call0 _xtensa_context_save
/* Save current SP before (possibly) overwriting it, it's the register
save
* area. This value will be used later by dispatch_c_isr to retrieve the
@@ -528,13 +525,13 @@ _xtensa_level3_handler:
/* Restore only level-specific regs (the rest were already restored) */
- l32i a0, a2, (4 * REG_PS) /* Retrieve
interruptee's PS */
+ l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */
wsr a0, EPS_3
- l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
+ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
wsr a0, EPC_3
- l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Remove interrupt
stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
rsync
/* Ensure EPS and EPC written */
/* Return from interrupt. RFI restores the PS from EPS_3 and jumps to
@@ -562,6 +559,7 @@ _xtensa_level4_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_4 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
#ifdef CONFIG_XTENSA_INTBACKTRACE
wsr sp, EXCSAVE_4
@@ -569,9 +567,7 @@ _xtensa_level4_handler:
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
- call0 _xtensa_context_save /* Save full register
state */
+ call0 _xtensa_context_save
/* Save current SP before (possibly) overwriting it, it's the register
save
* area. This value will be used later by dispatch_c_isr to retrieve the
@@ -606,13 +602,13 @@ _xtensa_level4_handler:
/* Restore only level-specific regs (the rest were already restored) */
- l32i a0, a2, (4 * REG_PS) /* Retrieve
interruptee's PS */
+ l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */
wsr a0, EPS_4
- l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
+ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
wsr a0, EPC_4
- l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Remove interrupt
stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
rsync
/* Ensure EPS and EPC written */
/* Return from interrupt. RFI restores the PS from EPS_4 and jumps to
@@ -640,6 +636,7 @@ _xtensa_level5_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_5 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
#ifdef CONFIG_XTENSA_INTBACKTRACE
wsr sp, EXCSAVE_5
@@ -647,9 +644,7 @@ _xtensa_level5_handler:
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
- call0 _xtensa_context_save /* Save full register
state */
+ call0 _xtensa_context_save
/* Save current SP before (possibly) overwriting it, it's the register
save
* area. This value will be used later by dispatch_c_isr to retrieve the
@@ -684,13 +679,13 @@ _xtensa_level5_handler:
/* Restore only level-specific regs (the rest were already restored) */
- l32i a0, a2, (4 * REG_PS) /* Retrieve
interruptee's PS */
+ l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */
wsr a0, EPS_5
- l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
+ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
wsr a0, EPC_5
- l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Remove interrupt
stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
rsync
/* Ensure EPS and EPC written */
/* Return from interrupt. RFI restores the PS from EPS_5 and jumps to
@@ -718,6 +713,7 @@ _xtensa_level6_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_6 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
#ifdef CONFIG_XTENSA_INTBACKTRACE
wsr sp, EXCSAVE_6
@@ -725,8 +721,6 @@ _xtensa_level6_handler:
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
call0 _xtensa_context_save /* Save full register
state */
/* Save current SP before (possibly) overwriting it, it's the register
save
@@ -762,13 +756,13 @@ _xtensa_level6_handler:
/* Restore only level-specific regs (the rest were already restored) */
- l32i a0, a2, (4 * REG_PS) /* Retrieve
interruptee's PS */
+ l32i a0, a2, (4 * REG_PS) /* Retrieve interruptee's PS */
wsr a0, EPS_6
- l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
+ l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
wsr a0, EPC_6
- l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Remove interrupt
stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
rsync
/* Ensure EPS and EPC written */
/* Return from interrupt. RFI restores the PS from EPS_6 and jumps to
diff --git a/arch/xtensa/src/common/xtensa_panic.S
b/arch/xtensa/src/common/xtensa_panic.S
index 6a45d01..eec2dcf 100644
--- a/arch/xtensa/src/common/xtensa_panic.S
+++ b/arch/xtensa/src/common/xtensa_panic.S
@@ -127,7 +127,6 @@ _xtensa_panic:
*/
s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
call0 _xtensa_context_save /* Save full register
state */
/* Dispatch the sycall as with other interrupts. */
diff --git a/arch/xtensa/src/common/xtensa_user_handler.S
b/arch/xtensa/src/common/xtensa_user_handler.S
index 4e2eda5..b03dfae 100644
--- a/arch/xtensa/src/common/xtensa_user_handler.S
+++ b/arch/xtensa/src/common/xtensa_user_handler.S
@@ -218,6 +218,7 @@ _xtensa_user_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_1 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
/* Save EXCCAUSE and EXCVADDR into the user frame */
@@ -228,8 +229,6 @@ _xtensa_user_handler:
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
call0 _xtensa_context_save /* Save full register
state */
/* Save current SP before (possibly) overwriting it,
@@ -298,8 +297,8 @@ _xtensa_user_handler:
l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
wsr a0, EPC_1
l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Remove interrupt
stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt
stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2
*/
rsync
/* Ensure PS and EPC written */
/* Return from exception. RFE returns from either the
UserExceptionVector
@@ -337,9 +336,7 @@ _xtensa_syscall_handler:
s32i a0, sp, (4 * REG_PS)
rsr a0, EXCSAVE_1 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
-
- s32i a2, sp, (4 * REG_A2) /* Save interruptee's
A2 */
- s32i a3, sp, (4 * REG_A3) /* Save interruptee's
A3 */
+ s32i a2, sp, (4 * REG_A2)
/* Save rest of interrupt context. */
@@ -430,8 +427,8 @@ _xtensa_syscall_handler:
l32i a0, a2, (4 * REG_PC) /* Retrieve
interruptee's PC */
wsr a0, EPC_1
l32i a0, a2, (4 * REG_A0) /* Retrieve
interruptee's A0 */
- l32i sp, a2, (4 * REG_A1) /* Remove interrupt
stack frame */
- l32i a2, a2, (4 * REG_A2) /* Retrieve
interruptee's A2 */
+ l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt
stack frame */
+ l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2
*/
rsync
/* Ensure PS and EPC written */
/* Return from exception. RFE returns from either the
UserExceptionVector
@@ -502,11 +499,10 @@ _xtensa_coproc_handler:
s32i a0, sp, (4 * REG_PC)
rsr a0, EXCSAVE_1 /* Save
interruptee's a0 */
s32i a0, sp, (4 * REG_A0)
+ s32i a2, sp, (4 * REG_A2)
/* Save rest of interrupt context. */
- s32i a2, sp, (4 * REG_A2)
- s32i a3, sp, (4 * REG_A3)
call0 _xtensa_context_save /* Save full register
state */
/* Switch to an interrupt stack if we have one */
