lipan118 edited a comment on pull request #5523:
URL: https://github.com/apache/incubator-nuttx/pull/5523#issuecomment-1061343686
> CONFIG_ETH0_PHY_DP83848C=y now implies the pin is wired to the SoC as an
interrupt, whenever the DP83848C PHY is used. This may not be the case, hence
the comment about it being a board config related setting.
>
> I would imagine if the PHY interrupt pin is not wired to the SoC it would
not be an issue for it to be configured unless this pin can be used for
something else and it is:
>
> 7.2.1.3.1 Power Down and Interrupt The Power Down and Interrupt functions
are multiplexed on pin 7 of the device. By default, this pin functions as a
power-down input and the interrupt function is disabled. Setting bit 0 (INT_OE)
of MICR (0x11h) will configure the pin as an active low interrupt output.
>
> So this needs more configuration options to deconflict the setting.
7.2.1.3.1.2 Interrupt Mechanisms
The interrupt function is controlled through register access. All interrupt
sources are disabled by default.
Setting bit 1 (INTEN) of MICR (0x11h) will enable interrupts to be output,
dependent on the interrupt mask
set in the lower byte of the MISR (0x12h). The PWRDOWN_INT pin is
asynchronously asserted low when
an interrupt condition occurs. The source of the interrupt can be determined
by reading the upper byte of
the MISR. One or more bits in the MISR will be set, denoting all currently
pending interrupts. Reading of
the MISR clears ALL pending interrupts.
Example: To generate an interrupt on a change of link status or on a change
of energy detect power state,
the steps would be:
• Write 0003h to MICR to set INTEN and INT_OE
• Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN
• Monitor PWRDOWN_INT pin
When PWRDOWN_INT pin asserts low, the user would read the MISR register to
see if the ED_INT or
LINK_INT bits are set, for example, which source caused the interrupt. After
reading the MISR, the
interrupt bits should clear and the PWRDOWN_INT pin will deassert.
1 • Write 0003h to MICR to set INTEN and INT_OE
`#ifdef CONFIG_ETH0_PHY_DP83848C
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_DP83848C_MICR,
MII_DP83848C_INT_EN | MII_DP83848C_INT_OEN);
#endif
`
2 • Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN
`
# define MII_INT_REG MII_DP83848C_MISR
# define MII_INT_SETEN MII_DP83848C_LINK_INT_EN
# define MII_INT_CLREN 0
`
`
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_INT_REG,
(phyval & ~MII_INT_CLREN) | MII_INT_SETEN);
`
3 • Monitor PWRDOWN_INT pin
related to pin connection. if you do not wired to the soc with dp83848c
interrupt ,you do not need monitor phy link status, This part of the code will
not affect. because
`
#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
static int stm32_phyintenable(struct stm32_ethmac_s *priv)
{
uint16_t phyval;
int ret;
ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_INT_REG, &phyval);
if (ret == OK)
{
/* Enable link up/down interrupts */
#ifdef CONFIG_ETH0_PHY_DP83848C
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_DP83848C_MICR,
MII_DP83848C_INT_EN | MII_DP83848C_INT_OEN);
#endif
ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_INT_REG,
(phyval & ~MII_INT_CLREN) | MII_INT_SETEN);
}
return ret;
}
#endif
`
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