patacongo commented on a change in pull request #1728: URL: https://github.com/apache/incubator-nuttx/pull/1728#discussion_r489491169
########## File path: boards/arm/sama5/giant-board/src/sam_sdram.c ########## @@ -0,0 +1,572 @@ +/**************************************************************************** + * boards/arm/sama5/giant-board/src/sam_sdram.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <debug.h> + +#include "arm_arch.h" + +#include "sam_periphclks.h" +#include "hardware/sam_memorymap.h" +#include "hardware/sam_pmc.h" +#include "hardware/sam_sfr.h" +#include "hardware/sam_mpddrc.h" + +#include "giant-board.h" + +/* This file requires: + * + * CONFIG_SAMA5_DDRCS -- DRAM support is enabled, and + * !CONFIG_SAMA5_BOOT_SDRAM - We did not boot into SRAM. + */ + +#if defined(CONFIG_SAMA5_DDRCS) && !defined(CONFIG_SAMA5_BOOT_SDRAM) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SDRAM differences */ + +#if defined(CONFIG_GIANT_BOARD_W971GG6SB) + /* Used for SDRAM command handshaking */ + +# define DDR2_BA0 (1 << 26) +# define DDR2_BA1 (1 << 27) + +#else +# error Unknown SDRAM type +#endif + +/* The delay loop in sam_sdram_delay requires 6 core cycles per iteration. + * + * At 492MHz: + * + * (6 cycles/iteration) / (0.492 cycles/nanosecond) = + * 12.1951 nanoseconds per iteration + */ + +#define LOOP_GUARD 100 +# define CYCLES_TO_COUNT(cycles) (((cycles) / 6) + LOOP_GUARD) + +#if defined(CONFIG_GIANT_BOARD_492MHZ) +# define NSEC_TO_COUNT(nsec) ((((nsec) * 1000) / 12195) + LOOP_GUARD) +# define USEC_TO_COUNT(usec) ((((usec) * 1000000) / 12195) + LOOP_GUARD) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_sdram_delay + * + * Description: + * Precision delay function for SDRAM configuration. + * + * This delay loop requires 6 core cycles per iteration. The actual + * amount of time delayed will then vary with PCK. + * + ****************************************************************************/ + +static inline void sam_sdram_delay(unsigned int loops) +{ + volatile unsigned int i; + + for (i = 0; i < loops; i++) + { + asm("nop"); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_sdram_config + * + * Description: + * Configures DDR2 (W971GG6SB) + * + * TODO: test (so far only booting into SDRAM has been tested using U-Boot) + * + * Per the SAMA5D-Xplained User guide: + * "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte). + * The board includes 2 Gbits of on-board soldered DDR2 (double data rate) + * SDRAM. The footprints can also host two DDR2(MT47H128M16RT) from Micron + * for a total of 512 MBytes of DDR2 memory. + * The memory bus is 32 bits wide and operates with a frequency of up + * to 166 MHz." + * + * From the Atmel Code Example: + * MT47H64M16HR : 8 Meg x 16 x 8 banks + * Refresh count: 8K + * Row address: A[12:0] (8K) + * Column address A[9:0] (1K) + * Bank address BA[2:0] a(24,25) (8) + * + * This logic was taken from Atmel sample code for the SAMA5D3x-EK. + * + * Input Parameters: + * devtype - Either DDRAM_MT47H128M16RT or DDRAM_MT47H64M16HR + * + * Assumptions: + * The DDR memory regions is configured as strongly ordered memory. When + * we complete initialization of SDRAM and it is ready for use, we will + * make DRAM into normal memory. + * + ****************************************************************************/ + +void sam_sdram_config(void) +{ + volatile uint8_t *ddr = (uint8_t *)SAM_DDRCS_VSECTION; + uint32_t regval; + + /* Enable x2 clocking to the MPDDRC */ + + sam_mpddrc_enableclk(); + + /* Enable DDR clocking */ + + regval = getreg32(SAM_PMC_SCER); + regval |= PMC_DDRCK; + putreg32(regval, SAM_PMC_SCER); + + /* Clear the low power register */ + + putreg32(0, SAM_MPDDRC_LPR); + + /* Enable autofresh during calibration (undocumented) */ + + regval = getreg32(SAM_MPDDRC_HS); + regval |= MPDDRC_HS_AUTOREFRESH_CAL; + putreg32(regval, SAM_MPDDRC_HS); + + /* Force DDR_DQ and DDR_DQS input buffer always on */ + + regval = getreg32(SAM_SFR_DDRCFG); + regval |= SFR_FDQIEN | SFR_FDQSIEN; + putreg32(regval, SAM_SFR_DDRCFG); + + /* Configure the slave offset register */ + + regval = MPDDRC_DLL_SOR_S0OFF(1) | /* DLL Slave 0 Delay Line Offset */ + MPDDRC_DLL_SOR_S1OFF(0) | /* DLL Slave 1 Delay Line Offset */ + MPDDRC_DLL_SOR_S2OFF(1) | /* DLL Slave 2 Delay Line Offset */ + MPDDRC_DLL_SOR_S3OFF(1); /* DLL Slave 3 Delay Line Offset */ + putreg32(regval, SAM_MPDDRC_DLL_SOR); + + /* Configure the master offset register (including upper mystery bits) */ + + regval = MPDDRC_DLL_MOR_MOFF(7) | /* DLL Master Delay Line Offset */ + MPDDRC_DLL_MOR_CLK90OFF(31) | /* DLL CLK90 Delay Line Offset */ + MPDDRC_DLL_MOR_SELOFF | /* DLL Offset Selection */ + MPDDRC_DLL_MOR_KEY; /* Undocumented key */ + putreg32(regval, SAM_MPDDRC_DLL_MOR); + + /* Configure the I/O calibration register */ + + regval = getreg32(SAM_MPDDRC_IO_CALIBR); + regval &= ~(MPDDRC_IO_CALIBR_RDIV_MASK | MPDDRC_IO_CALIBR_TZQIO_MASK); + regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); + putreg32(regval, SAM_MPDDRC_IO_CALIBR); + + /* Force DDR_DQ and DDR_DQS input buffer always on */ + + putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG); + + /* Step 1: Program the memory device type + * + * DBW = 0 (32-bit bus wide) + * Memory Device = DDR2-SDRAM + */ + + putreg32(MPDDRC_MD_DDR2_SDRAM, SAM_MPDDRC_MD); + + /* Step 2: Program the features of DDR2-SDRAM device into the Timing + * Register + */ + + /* SAMA5D27D1G uses Winbond W971GG6SB 1GB DDR2 RAM + * + * See datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Plus-DDR2-LPDDR2-System-in-Package-(SIP)-60001484b.pdf Review comment: ```suggestion * See datasheet http://ww1.microchip.com/downloads/en/DeviceDoc/ * SAMA5D2-Plus-DDR2-LPDDR2-System-in-Package-(SIP)-60001484b.pdf ``` ---------------------------------------------------------------- This is an automated message from the Apache Git Service. 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