(nuttx) 03/05: esp32[c6|h2|s2|s3]: Assign Edge/Level GPIO pin numbers when in Quadrature Encoder mode

Fri, 16 May 2025 07:12:32 -0700 

This is an automated email from the ASF dual-hosted git repository.

acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git

commit 3e100e3c869a619d4c49d31e8a109a688818f8d8
Author: Martin Vajnar <martin.vaj...@gmail.com>
AuthorDate: Sun Apr 27 16:05:56 2025 +0200

    esp32[c6|h2|s2|s3]: Assign Edge/Level GPIO pin numbers when in Quadrature 
Encoder mode
    
    Only 2 pins are needed in this mode for both channels. The wiring
    is such that Edge and Level pins are cross-connected for both
    channels.
---
 boards/risc-v/esp32c6/common/src/esp_board_pcnt.c  | 38 ++++++++++++++++++++--
 boards/risc-v/esp32h2/common/src/esp_board_pcnt.c  | 38 ++++++++++++++++++++--
 boards/xtensa/esp32/common/src/esp32_board_pcnt.c  | 38 ++++++++++++++++++++--
 .../xtensa/esp32s2/common/src/esp32s2_board_pcnt.c | 38 ++++++++++++++++++++--
 .../xtensa/esp32s3/common/src/esp32s3_board_pcnt.c | 38 ++++++++++++++++++++--
 5 files changed, 175 insertions(+), 15 deletions(-)

diff --git a/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c 
b/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
index 81e3938fd9..c8d50ae4b0 100644
--- a/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
+++ b/boards/risc-v/esp32c6/common/src/esp_board_pcnt.c
@@ -194,14 +194,22 @@ int board_pcnt_initialize(void)
   };
 
 #ifdef CONFIG_ESP_PCNT_U0
+#ifdef CONFIG_ESP_PCNT_U0_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
-#ifdef CONFIG_ESP_PCNT_TEST_MODE
-  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
-#endif
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+#endif
+#ifdef CONFIG_ESP_PCNT_TEST_MODE
+  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
+#endif
 #ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -230,11 +238,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U1
+#ifdef CONFIG_ESP_PCNT_U1_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -263,11 +279,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U2
+#ifdef CONFIG_ESP_PCNT_U2_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -297,11 +321,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U3
+#ifdef CONFIG_ESP_PCNT_U3_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
   glitch_threshold = 0;
 #else
diff --git a/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c 
b/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
index a0d31a9a5f..bfa5620208 100644
--- a/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
+++ b/boards/risc-v/esp32h2/common/src/esp_board_pcnt.c
@@ -194,14 +194,22 @@ int board_pcnt_initialize(void)
   };
 
 #ifdef CONFIG_ESP_PCNT_U0
+#ifdef CONFIG_ESP_PCNT_U0_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
-#ifdef CONFIG_ESP_PCNT_TEST_MODE
-  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
-#endif
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+#endif
+#ifdef CONFIG_ESP_PCNT_TEST_MODE
+  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
+#endif
 #ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -230,11 +238,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U1
+#ifdef CONFIG_ESP_PCNT_U1_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -263,11 +279,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U2
+#ifdef CONFIG_ESP_PCNT_U2_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -297,11 +321,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U3
+#ifdef CONFIG_ESP_PCNT_U3_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
   glitch_threshold = 0;
 #else
diff --git a/boards/xtensa/esp32/common/src/esp32_board_pcnt.c 
b/boards/xtensa/esp32/common/src/esp32_board_pcnt.c
index 722db97139..018d23216e 100644
--- a/boards/xtensa/esp32/common/src/esp32_board_pcnt.c
+++ b/boards/xtensa/esp32/common/src/esp32_board_pcnt.c
@@ -193,14 +193,22 @@ int board_pcnt_initialize(void)
   };
 
 #ifdef CONFIG_ESP_PCNT_U0
+#ifdef CONFIG_ESP_PCNT_U0_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
-#ifdef CONFIG_ESP_PCNT_TEST_MODE
-  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
-#endif
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+#endif
+#ifdef CONFIG_ESP_PCNT_TEST_MODE
+  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
+#endif
 #ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -229,11 +237,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U1
+#ifdef CONFIG_ESP_PCNT_U1_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -262,11 +278,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U2
+#ifdef CONFIG_ESP_PCNT_U2_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -296,11 +320,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U3
+#ifdef CONFIG_ESP_PCNT_U3_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
   glitch_threshold = 0;
 #else
diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c 
b/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c
index 5629f9c899..cbd7c49b78 100644
--- a/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c
+++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_pcnt.c
@@ -193,14 +193,22 @@ int board_pcnt_initialize(void)
   };
 
 #ifdef CONFIG_ESP_PCNT_U0
+#ifdef CONFIG_ESP_PCNT_U0_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
-#ifdef CONFIG_ESP_PCNT_TEST_MODE
-  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
-#endif
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+#endif
+#ifdef CONFIG_ESP_PCNT_TEST_MODE
+  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
+#endif
 #ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -229,11 +237,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U1
+#ifdef CONFIG_ESP_PCNT_U1_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -262,11 +278,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U2
+#ifdef CONFIG_ESP_PCNT_U2_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -296,11 +320,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U3
+#ifdef CONFIG_ESP_PCNT_U3_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
   glitch_threshold = 0;
 #else
diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c 
b/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c
index 916b23a06a..47621db8e4 100644
--- a/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c
+++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_pcnt.c
@@ -193,14 +193,22 @@ int board_pcnt_initialize(void)
   };
 
 #ifdef CONFIG_ESP_PCNT_U0
+#ifdef CONFIG_ESP_PCNT_U0_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH0_LEVEL_PIN;
-#ifdef CONFIG_ESP_PCNT_TEST_MODE
-  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
-#endif
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U0_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U0_CH1_LEVEL_PIN;
+#endif
+#ifdef CONFIG_ESP_PCNT_TEST_MODE
+  chan0_cfg.flags = ESP_PCNT_CHAN_IO_LOOPBACK;
+#endif
 #ifndef CONFIG_ESP_PCNT_U0_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -229,11 +237,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U1
+#ifdef CONFIG_ESP_PCNT_U1_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U1_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U1_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U1_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -262,11 +278,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U2
+#ifdef CONFIG_ESP_PCNT_U2_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U2_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U2_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U2_FILTER_EN
   glitch_threshold = 0;
 #else
@@ -296,11 +320,19 @@ int board_pcnt_initialize(void)
 #endif
 
 #ifdef CONFIG_ESP_PCNT_U3
+#ifdef CONFIG_ESP_PCNT_U3_QE
+  chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+  chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+
+  chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+  chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
+#else
   chan0_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH0_EDGE_PIN;
   chan0_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH0_LEVEL_PIN;
 
   chan1_cfg.edge_gpio_num = CONFIG_ESP_PCNT_U3_CH1_EDGE_PIN;
   chan1_cfg.level_gpio_num = CONFIG_ESP_PCNT_U3_CH1_LEVEL_PIN;
+#endif
 #ifndef CONFIG_ESP_PCNT_U3_FILTER_EN
   glitch_threshold = 0;
 #else

Reply via email to