leocafonso commented on code in PR #15892: URL: https://github.com/apache/nuttx/pull/15892#discussion_r1966614259
########## arch/arm/include/ra/ra4m1_irq.h: ########## @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/arm/include/ra4m1/ra4m1_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_RA_RA4M1_IRQ_H +#define __ARCH_ARM_INCLUDE_RA_RA4M1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include <nuttx/config.h> +#include <nuttx/irq.h> +#include <arch/ra/chip.h> +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + + +/* Total number of IRQ numbers */ +# define RA_IRQ_IELSR0 (RA_IRQ_FIRST + 0) /* 0: Event selected in the ICU.IELSR0 register */ +# define RA_IRQ_IELSR1 (RA_IRQ_FIRST + 1) /* 1: Event selected in the ICU.IELSR1 register */ +# define RA_IRQ_IELSR2 (RA_IRQ_FIRST + 2) /* 2: Event selected in the ICU.IELSR2 register */ +# define RA_IRQ_IELSR3 (RA_IRQ_FIRST + 3) /* 3: Event selected in the ICU.IELSR3 register */ +# define RA_IRQ_IELSR4 (RA_IRQ_FIRST + 4) /* 4: Event selected in the ICU.IELSR4 register */ +# define RA_IRQ_IELSR5 (RA_IRQ_FIRST + 5) /* 5: Event selected in the ICU.IELSR5 register */ +# define RA_IRQ_IELSR6 (RA_IRQ_FIRST + 6) /* 6: Event selected in the ICU.IELSR6 register */ +# define RA_IRQ_IELSR7 (RA_IRQ_FIRST + 7) /* 7: Event selected in the ICU.IELSR7 register */ +# define RA_IRQ_IELSR8 (RA_IRQ_FIRST + 8) /* 8: Event selected in the ICU.IELSR8 register */ +# define RA_IRQ_IELSR9 (RA_IRQ_FIRST + 9) /* 9: Event selected in the ICU.IELSR9 register */ +# define RA_IRQ_IELSR10 (RA_IRQ_FIRST + 10) /* 10: Event selected in the ICU.IELSR10 register */ +# define RA_IRQ_IELSR11 (RA_IRQ_FIRST + 11) /* 11: Event selected in the ICU.IELSR11 register */ +# define RA_IRQ_IELSR12 (RA_IRQ_FIRST + 12) /* 12: Event selected in the ICU.IELSR12 register */ +# define RA_IRQ_IELSR13 (RA_IRQ_FIRST + 13) /* 13: Event selected in the ICU.IELSR13 register */ +# define RA_IRQ_IELSR14 (RA_IRQ_FIRST + 14) /* 14: Event selected in the ICU.IELSR14 register */ +# define RA_IRQ_IELSR15 (RA_IRQ_FIRST + 15) /* 15: Event selected in the ICU.IELSR15 register */ +# define RA_IRQ_IELSR16 (RA_IRQ_FIRST + 16) /* 16: Event selected in the ICU.IELSR16 register */ +# define RA_IRQ_IELSR17 (RA_IRQ_FIRST + 17) /* 17: Event selected in the ICU.IELSR17 register */ +# define RA_IRQ_IELSR18 (RA_IRQ_FIRST + 18) /* 18: Event selected in the ICU.IELSR18 register */ +# define RA_IRQ_IELSR19 (RA_IRQ_FIRST + 19) /* 19: Event selected in the ICU.IELSR19 register */ +# define RA_IRQ_IELSR20 (RA_IRQ_FIRST + 20) /* 20: Event selected in the ICU.IELSR20 register */ +# define RA_IRQ_IELSR21 (RA_IRQ_FIRST + 21) /* 21: Event selected in the ICU.IELSR21 register */ +# define RA_IRQ_IELSR22 (RA_IRQ_FIRST + 22) /* 22: Event selected in the ICU.IELSR22 register */ +# define RA_IRQ_IELSR23 (RA_IRQ_FIRST + 23) /* 23: Event selected in the ICU.IELSR23 register */ +# define RA_IRQ_IELSR24 (RA_IRQ_FIRST + 24) /* 24: Event selected in the ICU.IELSR24 register */ +# define RA_IRQ_IELSR25 (RA_IRQ_FIRST + 25) /* 25: Event selected in the ICU.IELSR25 register */ +# define RA_IRQ_IELSR26 (RA_IRQ_FIRST + 26) /* 26: Event selected in the ICU.IELSR26 register */ +# define RA_IRQ_IELSR27 (RA_IRQ_FIRST + 27) /* 27: Event selected in the ICU.IELSR27 register */ +# define RA_IRQ_IELSR28 (RA_IRQ_FIRST + 28) /* 28: Event selected in the ICU.IELSR28 register */ +# define RA_IRQ_IELSR29 (RA_IRQ_FIRST + 29) /* 29: Event selected in the ICU.IELSR29 register */ +# define RA_IRQ_IELSR30 (RA_IRQ_FIRST + 30) /* 30: Event selected in the ICU.IELSR30 register */ +# define RA_IRQ_IELSR31 (RA_IRQ_FIRST + 31) /* 31: Event selected in the ICU.IELSR31 register */ +# define RA_IRQ_NEXTINT (32) + +#if (CONFIG_RA_SCI0_UART) +#define SCI0_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full +#define SCI0_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty +#define SCI0_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end +#define SCI0_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error +#endif + +#if (CONFIG_RA_SCI1_UART) +#define SCI1_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full +#define SCI1_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty +#define SCI1_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end +#define SCI1_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error +#endif + +#if (CONFIG_RA_SCI2_UART) +#define SCI2_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full +#define SCI2_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty +#define SCI2_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end +#define SCI2_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error +#endif + +#if (CONFIG_RA_SCI9_UART) +#define SCI9_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full +#define SCI9_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty +#define SCI9_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end +#define SCI9_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error Review Comment: I missed that. I started using the pre-commit tool and forgot to run it on the entire diff after squashing old commits. ########## arch/arm/src/ra/hardware/ra_gpio.h: ########## @@ -0,0 +1,188 @@ +/**************************************************************************** + * arch/arm/src/ra/hardware/ra_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H +#define __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "hardware/ra_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define R_PORT_PCNTR1_OFFSET 0x0000 /* Port Control Register 1 (32-bits) */ +#define R_PORT_PODR_OFFSET 0x0000 /* Pmn Output Data (16-bits) */ +#define R_PORT_PDR_OFFSET 0x0002 /* Pmn Direction (16-bits) */ +#define R_PORT_PCNTR2_OFFSET 0x0004 /* Port Control Register 2 (32-bits) */ +#define R_PORT_EIDR_OFFSET 0x0004 /* Port Event Input Data (16-bits) */ +#define R_PORT_PIDR_OFFSET 0x0006 /* Pmn State (16-bits) */ +#define R_PORT_PCNTR3_OFFSET 0x0008 /* Port Control Register 3 (32-bits) */ +#define R_PORT_PORR_OFFSET 0x0008 /* Pmn Output Reset (16-bits) */ +#define R_PORT_POSR_OFFSET 0x000a /* Pmn Output Set (16-bits) */ +#define R_PORT_PCNTR4_OFFSET 0x000c /* Port Control Register 3 (32-bits) */ +#define R_PORT_EORR_OFFSET 0x000c /* Pmn Event Output Set (16-bits) */ +#define R_PORT_EOSR_OFFSET 0x000e /* Pmn Output Reset (16-bits) */ + +#define R_PORT_OFFSET 0x0020 /* Relative Port Offset */ + +/* Register Addresses *******************************************************/ + +#define PORT0 (0) +#define PORT1 (1) +#define PORT2 (2) +#define PORT3 (3) +#define PORT4 (4) +#define PORT5 (5) +#define PORT6 (6) +#define PORT7 (7) +#define PORT8 (8) +#define PORT9 (9) + +#define PIN0 (0) +#define PIN1 (1) +#define PIN2 (2) +#define PIN3 (3) +#define PIN4 (4) +#define PIN5 (5) +#define PIN6 (6) +#define PIN7 (7) +#define PIN8 (8) +#define PIN9 (9) +#define PIN10 (10) +#define PIN11 (11) +#define PIN12 (12) +#define PIN13 (13) +#define PIN14 (14) +#define PIN15 (15) + +/* Relative PORT Registers */ + +# define R_PORT_PCNTR1(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR1_OFFSET) +# define R_PORT_PODR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PODR_OFFSET) +# define R_PORT_PDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PDR_OFFSET) +# define R_PORT_PCNTR2(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR2_OFFSET) +# define R_PORT_EIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_EIDR_OFFSET) +# define R_PORT_PIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PIDR_OFFSET) +# define R_PORT_PCNTR3(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR3_OFFSET) +# define R_PORT_PORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PORR_OFFSET) +# define R_PORT_POSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_POSR_OFFSET) +# define R_PORT_PCNTR4(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_PCNTR4_OFFSET) +# define R_PORT_EORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_EORR_OFFSET) +# define R_PORT_EOSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET + R_PORT_EOSR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Port Control Register 1 (32-bits) */ + +#define R_PORT_PCNTR1_PODR_SHIFT (16) /* 10000: Pmn Output Data */ +#define R_PORT_PCNTR1_PODR_MASK (0xffff) +#define R_PORT_PCNTR1_PDR_SHIFT (0) /* 01: Pmn Direction */ +#define R_PORT_PCNTR1_PDR_MASK (0xffff) Review Comment: @acassis, I have aligned all the hardware related files. -- This is an automated message from the Apache Git Service. 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