acassis commented on code in PR #15892:
URL: https://github.com/apache/nuttx/pull/15892#discussion_r1966490145
##########
Documentation/platforms/arm/ra4m1/boards/arduino-r4-minima/index.rst:
##########
@@ -0,0 +1,100 @@
+=================
+Arduino R4 Minima
+=================
+
Review Comment:
Please include the board picture, see other board with image for reference.
##########
arch/arm/Kconfig:
##########
@@ -1155,6 +1160,7 @@ config ARCH_CHIP
default "nrf53" if ARCH_CHIP_NRF53
default "nrf91" if ARCH_CHIP_NRF91
default "nuc1xx" if ARCH_CHIP_NUC1XX
+ default "ra" if ARCH_CHIP_RA
Review Comment:
@leocafonso I suggest to use "ra4" because there are many ra architectures
and families (RA0 [RA0E1], RA2 [RA2L1, RA2E1, RA2E2, RA2A1, RA4[...], ...).
Keep all inside a single "ra" will result in a code with too many #ifdefs and
that will make the code hard to read. I suggest to use same approach like
stm32, stm32f7, stm32h7, etc.
Source:
https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus
##########
arch/arm/src/ra/hardware/ra_option_setting.h:
##########
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_option_setting.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_pinmap.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_OFS0_OFFSET 0x0000 /* Option Function Select Register 0
(32-bits) */
+#define R_OFS1_OFFSET 0x0004 /* Option Function Select Register 1
(32-bits) */
+
+/* Register Addresses *******************************************************/
+
+/* Option Function Select Registers */
+
+# define R_OFS0 (R_OFS_BASE + R_OFS0_OFFSET)
+# define R_OFS1 (R_OFS_BASE + R_OFS1_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Option Function Select Register 0 */
+
+#define R_OFS0_RESERVED_31 (1 << 31)
/* Bit 31: Reserved */
+#define R_OFS0_WDTSTPCTL (1 << 30)
/* Bit 30: WDT Stop Control */
+#define R_OFS0_RESERVED_29 (1 << 29)
/* Bit 29: Reserved */
+#define R_OFS0_WDTRSTIRQS (1 << 28)
/* Bit 28: WDT Reset Interrupt Request Select*/
+#define R_OFS0_WDTRPSS_SHIFT (26)
/* Bit 27-26: WDT Window Start Position Select*/
+#define R_OFS0_WDTRPSS_MASK (3 << R_OFS0_WDTRPSS_SHIFT)
+# define R_OFS0_WDTRPSS_25 (0 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 25% */
+# define R_OFS0_WDTRPSS_50 (1 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 50% */
+# define R_OFS0_WDTRPSS_75 (2 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 75% */
+# define R_OFS0_WDTRPSS_100 (3 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 100% */
+#define R_OFS0_WDTRPES_SHIFT (24)
/* Bit 25-24: WDT Window End Position Select*/
+#define R_OFS0_WDTRPES_MASK (3 << R_OFS0_WDTRPES_SHIFT)
+# define R_OFS0_WDTRPES_75 (0 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 75% */
+# define R_OFS0_WDTRPES_50 (1 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 50% */
+# define R_OFS0_WDTRPES_25 (2 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 25% */
+# define R_OFS0_WDTRPES_0 (3 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 0% */
+#define R_OFS0_WDTCKS_SHIFT (20)
/* Bit 23-20: WDT Clock Frequency Division Ratio Select*/
+#define R_OFS0_WDTCKS_MASK (0xF << R_OFS0_WDTCKS_SHIFT)
+# define R_OFS0_WDTCKS_DIV_4 (1 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 4 */
+# define R_OFS0_WDTCKS_DIV_64 (4 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 64 */
+# define R_OFS0_WDTCKS_DIV_128 (15 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 128 */
+# define R_OFS0_WDTCKS_DIV_512 (6 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 512 */
+# define R_OFS0_WDTCKS_DIV_2048 (7 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 2048 */
+# define R_OFS0_WDTCKS_DIV_8192 (8 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 8192 */
+#define R_OFS0_WDTTOPS_SHIFT (18)
/* Bit 19-18: WDT Timeout Period Select */
+#define R_OFS0_WDTTOPS_MASK (3 << R_OFS0_WDTTOPS_SHIFT)
+# define R_OFS0_WDTTOPS_1024_CYCLES (0 << R_OFS0_WDTTOPS_SHIFT)
/* 1024 cycles */
+# define R_OFS0_WDTTOPS_4096_CYCLES (1 << R_OFS0_WDTTOPS_SHIFT)
/* 4096 cycles */
+# define R_OFS0_WDTTOPS_8192_CYCLES (2 << R_OFS0_WDTTOPS_SHIFT)
/* 8192 cycles */
+# define R_OFS0_WDTTOPS_16384_CYCLES (3 << R_OFS0_WDTTOPS_SHIFT)
/* 16384 cycles */
+#define R_OFS0_RESERVED_16_15_SHIFT (15)
/* Bit 16-15: Reserved */
+#define R_OFS0_RESERVED_16_15_MASK (3 << R_OFS0_RESERVED_16_15_SHIFT)
/* Bit 16-15: Reserved */
+#define R_OFS0_WDTSTRT (1 << 17)
/* Bit 17: WDT Start Mode Select */
+#define R_OFS0_IWDTSTPCTL (1 << 14)
/* Bit 14: IWDT Stop Control */
+#define R_OFS0_RESERVED_13 (1 << 13)
/* Bit 13: Reserved */
+#define R_OFS0_IWDTRSTIRQS (1 << 12)
/* Bit 12: IWDT Reset Interrupt Request Select */
+#define R_OFS0_IWDTRPSS_SHIFT (10)
/* Bit 11-10: IWDT Window Start Position Select */
+#define R_OFS0_IWDTRPSS_MASK (3 << R_OFS0_IWDTRPSS_SHIFT)
+# define R_OFS0_IWDTRPSS_25 (0 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 25% */
+# define R_OFS0_IWDTRPSS_50 (1 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 50% */
+# define R_OFS0_IWDTRPSS_75 (2 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 75% */
+# define R_OFS0_IWDTRPSS_100 (3 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 100% */
+#define R_OFS0_IWDTRPES_SHIFT (8)
/* Bit 9-8: IWDT Window End Position Select*/
+#define R_OFS0_IWDTRPES_MASK (3 << R_OFS0_IWDTRPES_SHIFT)
+# define R_OFS0_IWDTRPES_75 (0 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 75% */
+# define R_OFS0_IWDTRPES_50 (1 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 50% */
+# define R_OFS0_IWDTRPES_25 (2 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 25% */
+# define R_OFS0_IWDTRPES_0 (3 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 0% */
+#define R_OFS0_IWDTCKS_SHIFT (4)
/* Bit 7-4: IWDT Clock Frequency Division Ratio Select*/
+#define R_OFS0_IWDTCKS_MASK (0xF << R_OFS0_IWDTCKS_SHIFT)
+# define R_OFS0_IWDTCKS_DIV_1 (0 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 1 */
+# define R_OFS0_IWDTCKS_DIV_16 (2 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 16 */
+# define R_OFS0_IWDTCKS_DIV_32 (3 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 32 */
+# define R_OFS0_IWDTCKS_DIV_64 (4 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 64 */
+# define R_OFS0_IWDTCKS_DIV_128 (15 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 128 */
+# define R_OFS0_IWDTCKS_DIV_256 (5 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 256 */
+#define R_OFS0_IWDTTOPS_SHIFT (2)
/* Bit 3-2: IWDT Timeout Period Select */
Review Comment:
Align
##########
Documentation/platforms/arm/ra4m1/index.rst:
##########
@@ -0,0 +1,85 @@
+=============
+Renesas RA4M1
+=============
+
+Supported MCUs
+==============
+
+The following list includes MCUs from RA4M1 series and indicates whether
+they are supported in NuttX
+
+============= ======= ================
+MCU Support Note
+============= ======= ================
+R7FA4M1ABxCFP Yes
+R7FA4M1ABxCLJ No
+R7FA4M1ABxCFM Yes
+R7FA4M1ABxCNB No
+R7FA4M1ABxCFL Yes
+R7FA4M1ABxCNE No
+R7FA4M1ABxCNF No
+============= ======= ================
+
+Peripheral Support
+==================
+
+The following list indicates peripherals supported in NuttX:
+
+========== ======= =====================================
+Peripheral Support Notes
+========== ======= =====================================
+FLASH No
+CLOCK Yes Partially, just internal clock (HOCO)
+ICU Yes
+KINT No
+ELC No
+DTC No
+DMAC No
+GPT No
+AGT No
+RTC No
+WDT No
+IWDT No
+SCI No Just UART
Review Comment:
Please change to Yes, since you explain it only supports UART for now
##########
arch/arm/src/ra/hardware/ra_gpio.h:
##########
@@ -0,0 +1,188 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_PORT_PCNTR1_OFFSET 0x0000 /* Port Control Register 1
(32-bits) */
+#define R_PORT_PODR_OFFSET 0x0000 /* Pmn Output Data (16-bits) */
+#define R_PORT_PDR_OFFSET 0x0002 /* Pmn Direction (16-bits) */
+#define R_PORT_PCNTR2_OFFSET 0x0004 /* Port Control Register 2
(32-bits) */
+#define R_PORT_EIDR_OFFSET 0x0004 /* Port Event Input Data
(16-bits) */
+#define R_PORT_PIDR_OFFSET 0x0006 /* Pmn State (16-bits) */
+#define R_PORT_PCNTR3_OFFSET 0x0008 /* Port Control Register 3
(32-bits) */
+#define R_PORT_PORR_OFFSET 0x0008 /* Pmn Output Reset (16-bits)
*/
+#define R_PORT_POSR_OFFSET 0x000a /* Pmn Output Set (16-bits) */
+#define R_PORT_PCNTR4_OFFSET 0x000c /* Port Control Register 3
(32-bits) */
+#define R_PORT_EORR_OFFSET 0x000c /* Pmn Event Output Set
(16-bits) */
+#define R_PORT_EOSR_OFFSET 0x000e /* Pmn Output Reset (16-bits)
*/
+
+#define R_PORT_OFFSET 0x0020 /* Relative Port Offset */
+
+/* Register Addresses *******************************************************/
+
+#define PORT0 (0)
+#define PORT1 (1)
+#define PORT2 (2)
+#define PORT3 (3)
+#define PORT4 (4)
+#define PORT5 (5)
+#define PORT6 (6)
+#define PORT7 (7)
+#define PORT8 (8)
+#define PORT9 (9)
+
+#define PIN0 (0)
+#define PIN1 (1)
+#define PIN2 (2)
+#define PIN3 (3)
+#define PIN4 (4)
+#define PIN5 (5)
+#define PIN6 (6)
+#define PIN7 (7)
+#define PIN8 (8)
+#define PIN9 (9)
+#define PIN10 (10)
+#define PIN11 (11)
+#define PIN12 (12)
+#define PIN13 (13)
+#define PIN14 (14)
+#define PIN15 (15)
+
+/* Relative PORT Registers */
+
+# define R_PORT_PCNTR1(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR1_OFFSET)
+# define R_PORT_PODR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PODR_OFFSET)
+# define R_PORT_PDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PDR_OFFSET)
+# define R_PORT_PCNTR2(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR2_OFFSET)
+# define R_PORT_EIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_EIDR_OFFSET)
+# define R_PORT_PIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PIDR_OFFSET)
+# define R_PORT_PCNTR3(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR3_OFFSET)
+# define R_PORT_PORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PORR_OFFSET)
+# define R_PORT_POSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_POSR_OFFSET)
+# define R_PORT_PCNTR4(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR4_OFFSET)
+# define R_PORT_EORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_EORR_OFFSET)
+# define R_PORT_EOSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_EOSR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Port Control Register 1 (32-bits) */
+
+#define R_PORT_PCNTR1_PODR_SHIFT (16) /* 10000: Pmn Output Data
*/
+#define R_PORT_PCNTR1_PODR_MASK (0xffff)
+#define R_PORT_PCNTR1_PDR_SHIFT (0) /* 01: Pmn Direction */
+#define R_PORT_PCNTR1_PDR_MASK (0xffff)
+
+/* Pmn Output Data (16-bits) */
+
+#define R_PORT_PODR_PODR_SHIFT (0) /* 01: Pmn Output Data */
+#define R_PORT_PODR_PODR_MASK (0xffff)
+
+/* Pmn Direction (16-bits) */
+
+#define R_PORT_PDR_PDR_SHIFT (0) /* 01: Pmn Direction */
+#define R_PORT_PDR_PDR_MASK (0xffff)
+
+/* Port Control Register 2 (32-bits) */
+
+#define R_PORT_PCNTR2_EIDR_SHIFT (16) /* 10000: Pmn Event Input
Data */
+#define R_PORT_PCNTR2_EIDR_MASK (0xffff)
+#define R_PORT_PCNTR2_PIDR_SHIFT (0) /* 01: Pmn Input Data */
+#define R_PORT_PCNTR2_PIDR_MASK (0xffff)
+
+/* Port Event Input Data (16-bits) */
+
+#define R_PORT_EIDR_EIDR_SHIFT (0) /* 01: Pmn Event Input Data
*/
+#define R_PORT_EIDR_EIDR_MASK (0xffff)
+
+/* Pmn State (16-bits) */
+
+#define R_PORT_PIDR_PIDR_SHIFT (0) /* 01: Pmn Input Data */
+#define R_PORT_PIDR_PIDR_MASK (0xffff)
+
+/* Port Control Register 3 (32-bits) */
+
+#define R_PORT_PCNTR3_PORR_SHIFT (16) /* 10000: Pmn Output Reset
*/
+#define R_PORT_PCNTR3_PORR_MASK (0xffff)
+#define R_PORT_PCNTR3_POSR_SHIFT (0) /* 01: Pmn Output Set */
+#define R_PORT_PCNTR3_POSR_MASK (0xffff)
+
+/* Pmn Output Reset (16-bits) */
+
+#define R_PORT_PORR_PORR_SHIFT (0) /* 01: Pmn Output Reset */
+#define R_PORT_PORR_PORR_MASK (0xffff)
+
+/* Pmn Output Set (16-bits) */
+
+#define R_PORT_POSR_POSR_SHIFT (0) /* 01: Pmn Output Set */
+#define R_PORT_POSR_POSR_MASK (0xffff)
+
+/* Port Control Register 3 (32-bits) */
+
+#define R_PORT_PCNTR4_EORR_SHIFT (16) /* 10000: Pmn Event Output
Reset */
+#define R_PORT_PCNTR4_EORR_MASK (0xffff)
+#define R_PORT_PCNTR4_EOSR_SHIFT (0) /* 01: Pmn Event Output Set
*/
+#define R_PORT_PCNTR4_EOSR_MASK (0xffff)
+
+/* Pmn Event Output Set (16-bits) */
+
+#define R_PORT_EORR_EORR_SHIFT (0) /* 01: Pmn Event Output
Reset */
+#define R_PORT_EORR_EORR_MASK (0xffff)
+
+/* Pmn Output Reset (16-bits) */
+
+#define R_PORT_EOSR_EOSR_SHIFT (0) /* 01: Pmn Event Output Set
*/
+#define R_PORT_EOSR_EOSR_MASK (0xffff)
Review Comment:
Ditto
##########
arch/arm/include/ra/ra4m1_irq.h:
##########
@@ -0,0 +1,132 @@
+/****************************************************************************
+ * arch/arm/include/ra4m1/ra4m1_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_RA_RA4M1_IRQ_H
+#define __ARCH_ARM_INCLUDE_RA_RA4M1_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <arch/ra/chip.h>
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+
+/* Total number of IRQ numbers */
+# define RA_IRQ_IELSR0 (RA_IRQ_FIRST + 0) /* 0: Event selected in the
ICU.IELSR0 register */
+# define RA_IRQ_IELSR1 (RA_IRQ_FIRST + 1) /* 1: Event selected in the
ICU.IELSR1 register */
+# define RA_IRQ_IELSR2 (RA_IRQ_FIRST + 2) /* 2: Event selected in the
ICU.IELSR2 register */
+# define RA_IRQ_IELSR3 (RA_IRQ_FIRST + 3) /* 3: Event selected in the
ICU.IELSR3 register */
+# define RA_IRQ_IELSR4 (RA_IRQ_FIRST + 4) /* 4: Event selected in the
ICU.IELSR4 register */
+# define RA_IRQ_IELSR5 (RA_IRQ_FIRST + 5) /* 5: Event selected in the
ICU.IELSR5 register */
+# define RA_IRQ_IELSR6 (RA_IRQ_FIRST + 6) /* 6: Event selected in the
ICU.IELSR6 register */
+# define RA_IRQ_IELSR7 (RA_IRQ_FIRST + 7) /* 7: Event selected in the
ICU.IELSR7 register */
+# define RA_IRQ_IELSR8 (RA_IRQ_FIRST + 8) /* 8: Event selected in the
ICU.IELSR8 register */
+# define RA_IRQ_IELSR9 (RA_IRQ_FIRST + 9) /* 9: Event selected in the
ICU.IELSR9 register */
+# define RA_IRQ_IELSR10 (RA_IRQ_FIRST + 10) /* 10: Event selected in
the ICU.IELSR10 register */
+# define RA_IRQ_IELSR11 (RA_IRQ_FIRST + 11) /* 11: Event selected in
the ICU.IELSR11 register */
+# define RA_IRQ_IELSR12 (RA_IRQ_FIRST + 12) /* 12: Event selected in
the ICU.IELSR12 register */
+# define RA_IRQ_IELSR13 (RA_IRQ_FIRST + 13) /* 13: Event selected in
the ICU.IELSR13 register */
+# define RA_IRQ_IELSR14 (RA_IRQ_FIRST + 14) /* 14: Event selected in
the ICU.IELSR14 register */
+# define RA_IRQ_IELSR15 (RA_IRQ_FIRST + 15) /* 15: Event selected in
the ICU.IELSR15 register */
+# define RA_IRQ_IELSR16 (RA_IRQ_FIRST + 16) /* 16: Event selected in
the ICU.IELSR16 register */
+# define RA_IRQ_IELSR17 (RA_IRQ_FIRST + 17) /* 17: Event selected in
the ICU.IELSR17 register */
+# define RA_IRQ_IELSR18 (RA_IRQ_FIRST + 18) /* 18: Event selected in
the ICU.IELSR18 register */
+# define RA_IRQ_IELSR19 (RA_IRQ_FIRST + 19) /* 19: Event selected in
the ICU.IELSR19 register */
+# define RA_IRQ_IELSR20 (RA_IRQ_FIRST + 20) /* 20: Event selected in
the ICU.IELSR20 register */
+# define RA_IRQ_IELSR21 (RA_IRQ_FIRST + 21) /* 21: Event selected in
the ICU.IELSR21 register */
+# define RA_IRQ_IELSR22 (RA_IRQ_FIRST + 22) /* 22: Event selected in
the ICU.IELSR22 register */
+# define RA_IRQ_IELSR23 (RA_IRQ_FIRST + 23) /* 23: Event selected in
the ICU.IELSR23 register */
+# define RA_IRQ_IELSR24 (RA_IRQ_FIRST + 24) /* 24: Event selected in
the ICU.IELSR24 register */
+# define RA_IRQ_IELSR25 (RA_IRQ_FIRST + 25) /* 25: Event selected in
the ICU.IELSR25 register */
+# define RA_IRQ_IELSR26 (RA_IRQ_FIRST + 26) /* 26: Event selected in
the ICU.IELSR26 register */
+# define RA_IRQ_IELSR27 (RA_IRQ_FIRST + 27) /* 27: Event selected in
the ICU.IELSR27 register */
+# define RA_IRQ_IELSR28 (RA_IRQ_FIRST + 28) /* 28: Event selected in
the ICU.IELSR28 register */
+# define RA_IRQ_IELSR29 (RA_IRQ_FIRST + 29) /* 29: Event selected in
the ICU.IELSR29 register */
+# define RA_IRQ_IELSR30 (RA_IRQ_FIRST + 30) /* 30: Event selected in
the ICU.IELSR30 register */
+# define RA_IRQ_IELSR31 (RA_IRQ_FIRST + 31) /* 31: Event selected in
the ICU.IELSR31 register */
+# define RA_IRQ_NEXTINT (32)
+
+#if (CONFIG_RA_SCI0_UART)
+#define SCI0_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full
+#define SCI0_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty
+#define SCI0_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end
+#define SCI0_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error
+#endif
+
+#if (CONFIG_RA_SCI1_UART)
+#define SCI1_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full
+#define SCI1_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty
+#define SCI1_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end
+#define SCI1_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error
+#endif
+
+#if (CONFIG_RA_SCI2_UART)
+#define SCI2_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full
+#define SCI2_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty
+#define SCI2_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end
+#define SCI2_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error
+#endif
+
+#if (CONFIG_RA_SCI9_UART)
+#define SCI9_RXI (RA_IRQ_FIRST + __COUNTER__) // Receive data full
+#define SCI9_TXI (RA_IRQ_FIRST + __COUNTER__) // Transmit data empty
+#define SCI9_TEI (RA_IRQ_FIRST + __COUNTER__) // Transmit end
+#define SCI9_ERI (RA_IRQ_FIRST + __COUNTER__) // Receive error
Review Comment:
Please fix C++ comments
##########
arch/arm/src/ra/hardware/ra_gpio.h:
##########
@@ -0,0 +1,188 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_PORT_PCNTR1_OFFSET 0x0000 /* Port Control Register 1
(32-bits) */
+#define R_PORT_PODR_OFFSET 0x0000 /* Pmn Output Data (16-bits) */
+#define R_PORT_PDR_OFFSET 0x0002 /* Pmn Direction (16-bits) */
+#define R_PORT_PCNTR2_OFFSET 0x0004 /* Port Control Register 2
(32-bits) */
+#define R_PORT_EIDR_OFFSET 0x0004 /* Port Event Input Data
(16-bits) */
+#define R_PORT_PIDR_OFFSET 0x0006 /* Pmn State (16-bits) */
+#define R_PORT_PCNTR3_OFFSET 0x0008 /* Port Control Register 3
(32-bits) */
+#define R_PORT_PORR_OFFSET 0x0008 /* Pmn Output Reset (16-bits)
*/
+#define R_PORT_POSR_OFFSET 0x000a /* Pmn Output Set (16-bits) */
+#define R_PORT_PCNTR4_OFFSET 0x000c /* Port Control Register 3
(32-bits) */
+#define R_PORT_EORR_OFFSET 0x000c /* Pmn Event Output Set
(16-bits) */
+#define R_PORT_EOSR_OFFSET 0x000e /* Pmn Output Reset (16-bits)
*/
+
+#define R_PORT_OFFSET 0x0020 /* Relative Port Offset */
+
+/* Register Addresses *******************************************************/
+
+#define PORT0 (0)
+#define PORT1 (1)
+#define PORT2 (2)
+#define PORT3 (3)
+#define PORT4 (4)
+#define PORT5 (5)
+#define PORT6 (6)
+#define PORT7 (7)
+#define PORT8 (8)
+#define PORT9 (9)
+
+#define PIN0 (0)
+#define PIN1 (1)
+#define PIN2 (2)
+#define PIN3 (3)
+#define PIN4 (4)
+#define PIN5 (5)
+#define PIN6 (6)
+#define PIN7 (7)
+#define PIN8 (8)
+#define PIN9 (9)
+#define PIN10 (10)
+#define PIN11 (11)
+#define PIN12 (12)
+#define PIN13 (13)
+#define PIN14 (14)
+#define PIN15 (15)
+
+/* Relative PORT Registers */
+
+# define R_PORT_PCNTR1(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR1_OFFSET)
+# define R_PORT_PODR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PODR_OFFSET)
+# define R_PORT_PDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PDR_OFFSET)
+# define R_PORT_PCNTR2(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR2_OFFSET)
+# define R_PORT_EIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_EIDR_OFFSET)
+# define R_PORT_PIDR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PIDR_OFFSET)
+# define R_PORT_PCNTR3(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR3_OFFSET)
+# define R_PORT_PORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PORR_OFFSET)
+# define R_PORT_POSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_POSR_OFFSET)
+# define R_PORT_PCNTR4(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_PCNTR4_OFFSET)
+# define R_PORT_EORR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_EORR_OFFSET)
+# define R_PORT_EOSR(port) (R_PORT0_BASE + (port)*R_PORT_OFFSET +
R_PORT_EOSR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Port Control Register 1 (32-bits) */
+
+#define R_PORT_PCNTR1_PODR_SHIFT (16) /* 10000: Pmn Output Data
*/
+#define R_PORT_PCNTR1_PODR_MASK (0xffff)
+#define R_PORT_PCNTR1_PDR_SHIFT (0) /* 01: Pmn Direction */
+#define R_PORT_PCNTR1_PDR_MASK (0xffff)
Review Comment:
Please align the right block
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUPT_PROTECT (1 << 0) /* 01: Protection of
register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+
+/* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUSA_MSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_MSPMPUSA_MSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Master MPU End Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUEA_MSPMPUEA (32 << 0) /* 01: Region end address
register Address where the region starts, for use in region determination.
NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_MSPMPUEA_MSPMPUEA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Peripheral MPU Override
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUOAD_KEY (8 << 8) /* 100: Key Code The data
written to these bits are not stored. */
+#define R_SPMON_PSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_PSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Peripheral MPU Control Register (32-bits) */
+
+#define R_SPMON_PSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_PSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Peripheral MPU Protection
+ * Type Register (16-bits)
+ */
+
+#define R_SPMON_PSPMPUPT_KEY (8 << 8) /* 100: Key Code The data
written to these bits are not stored. */
+#define R_SPMON_PSPMPUPT_KEY_MASK (0xff)
Review Comment:
Ditto
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
Review Comment:
Ditto
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUPT_PROTECT (1 << 0) /* 01: Protection of
register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+
+/* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUSA_MSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_MSPMPUSA_MSPMPUSA_MASK (0xffffffff)
Review Comment:
Ditto
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
Review Comment:
Please align
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUPT_PROTECT (1 << 0) /* 01: Protection of
register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+
+/* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUSA_MSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_MSPMPUSA_MSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Master MPU End Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUEA_MSPMPUEA (32 << 0) /* 01: Region end address
register Address where the region starts, for use in region determination.
NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_MSPMPUEA_MSPMPUEA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Peripheral MPU Override
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUOAD_KEY (8 << 8) /* 100: Key Code The data
written to these bits are not stored. */
+#define R_SPMON_PSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_PSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Peripheral MPU Control Register (32-bits) */
+
+#define R_SPMON_PSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_PSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Peripheral MPU Protection
+ * Type Register (16-bits)
+ */
+
+#define R_SPMON_PSPMPUPT_KEY (8 << 8) /* 100: Key Code The data
written to these bits are not stored. */
+#define R_SPMON_PSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_PSPMPUPT_PROTECT (1 << 0) /* 01: Protection register
*/
+
+/* Secure Protection Monitor Peripheral MPU Start
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUSA_PSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_PSPMPUSA_PSPMPUSA_MASK (0xffffffff)
Review Comment:
Ditto
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUPT_PROTECT (1 << 0) /* 01: Protection of
register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+
+/* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUSA_MSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_MSPMPUSA_MSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Master MPU End Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUEA_MSPMPUEA (32 << 0) /* 01: Region end address
register Address where the region starts, for use in region determination.
NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_MSPMPUEA_MSPMPUEA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Peripheral MPU Override
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUOAD_KEY (8 << 8) /* 100: Key Code The data
written to these bits are not stored. */
+#define R_SPMON_PSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_PSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Peripheral MPU Control Register (32-bits) */
+
+#define R_SPMON_PSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_PSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Peripheral MPU Protection
+ * Type Register (16-bits)
+ */
+
+#define R_SPMON_PSPMPUPT_KEY (8 << 8) /* 100: Key Code The data
written to these bits are not stored. */
+#define R_SPMON_PSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_PSPMPUPT_PROTECT (1 << 0) /* 01: Protection register
*/
+
+/* Secure Protection Monitor Peripheral MPU Start
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUSA_PSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_PSPMPUSA_PSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Peripheral MPU End Address Register (32-bits) */
+
+#define R_SPMON_PSPMPUEA_PSPMPUEA (32 << 0) /* 01: Region end address
register Address where the region starts, for use in region determination.
NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_PSPMPUEA_PSPMPUEA_MASK (0xffffffff)
Review Comment:
Ditto
##########
arch/arm/src/ra/hardware/ra_option_setting.h:
##########
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_option_setting.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_pinmap.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_OFS0_OFFSET 0x0000 /* Option Function Select Register 0
(32-bits) */
+#define R_OFS1_OFFSET 0x0004 /* Option Function Select Register 1
(32-bits) */
+
+/* Register Addresses *******************************************************/
+
+/* Option Function Select Registers */
+
+# define R_OFS0 (R_OFS_BASE + R_OFS0_OFFSET)
+# define R_OFS1 (R_OFS_BASE + R_OFS1_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Option Function Select Register 0 */
+
+#define R_OFS0_RESERVED_31 (1 << 31)
/* Bit 31: Reserved */
+#define R_OFS0_WDTSTPCTL (1 << 30)
/* Bit 30: WDT Stop Control */
+#define R_OFS0_RESERVED_29 (1 << 29)
/* Bit 29: Reserved */
+#define R_OFS0_WDTRSTIRQS (1 << 28)
/* Bit 28: WDT Reset Interrupt Request Select*/
Review Comment:
Please align the right block
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUPT_PROTECT (1 << 0) /* 01: Protection of
register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+
+/* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUSA_MSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_MSPMPUSA_MSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Master MPU End Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUEA_MSPMPUEA (32 << 0) /* 01: Region end address
register Address where the region starts, for use in region determination.
NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_MSPMPUEA_MSPMPUEA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Peripheral MPU Override
+ * Address Register (32-bits)
+ */
+
+#define R_SPMON_PSPMPUOAD_KEY (8 << 8) /* 100: Key Code The data
written to these bits are not stored. */
+#define R_SPMON_PSPMPUOAD_KEY_MASK (0xff)
Review Comment:
Ditto
##########
arch/arm/src/ra/hardware/ra_mpu.h:
##########
@@ -0,0 +1,210 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_mpu.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+#define __ARCH_ARM_SRC_RA4M1_HARDWARE_RA4M1_MPU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/ra4m1/chip.h>
+#include "ra4m1_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_MMPU_MMPUCTLA_OFFSET 0x0000
+#define R_MMPU_MMPUACA_OFFSET 0x0200
+#define R_MMPU_MMPUSA_OFFSET 0x0204
+#define R_MMPU_MMPUEA_OFFSET 0x0208
+#define R_MMPU_MMPUPTA_OFFSET 0x0102
+#define R_SMPU_SMPUCTL_OFFSET 0x0000
+#define R_SMPU_SMPUMBIU_OFFSET 0x0010
+#define R_SMPU_SMPUFBIU_OFFSET 0x0014
+#define R_SMPU_SMPUSRAM0_OFFSET 0x0018
+#define R_SMPU_SMPUPBIU_OFFSET 0x0020
+#define R_SPMON_MSPMPUOAD_OFFSET 0x0000
+#define R_SPMON_MSPMPUCTL_OFFSET 0x0004
+#define R_SPMON_MSPMPUPT_OFFSET 0x0006
+#define R_SPMON_MSPMPUSA_OFFSET 0x0008
+#define R_SPMON_MSPMPUEA_OFFSET 0x000c
+#define R_SPMON_PSPMPUOAD_OFFSET 0x0010
+#define R_SPMON_PSPMPUCTL_OFFSET 0x0014
+#define R_SPMON_PSPMPUPT_OFFSET 0x0016
+#define R_SPMON_PSPMPUSA_OFFSET 0x0018
+#define R_SPMON_PSPMPUEA_OFFSET 0x001c
+
+/* Register Addresses *******************************************************/
+
+#define R_MMPU_MMPUCTLA (R_MMPU_BASE +
R_MMPU_MMPUCTLA_OFFSET) /* MMPU Control Register A (32-bits) */
+#define R_MMPU_MMPUACA(p) (R_MMPU_BASE + R_MMPU_MMPUACA_OFFSET
+ (p)*0x0010) /* MMPU Access Control Register A (32-bits) */
+#define R_MMPU_MMPUSA(p) (R_MMPU_BASE + R_MMPU_MMPUSA_OFFSET
+ (p)*0x0010) /* MMPU Start Address Register A (32-bits) */
+#define R_MMPU_MMPUEA(p) (R_MMPU_BASE + R_MMPU_MMPUEA_OFFSET
+ (p)*0x0010) /* MMPU End Address Register A (32-bits) */
+#define R_MMPU_MMPUPTA (R_MMPU_BASE +
R_MMPU_MMPUPTA_OFFSET) /* MMPU Protection Type Register A
(16-bits) */
+#define R_SMPU_SMPUCTL (R_SMPU_BASE +
R_SMPU_SMPUCTL_OFFSET) /* SMPU Control Register (32-bits) */
+#define R_SMPU_SMPUMBIU (R_SMPU_BASE +
R_SMPU_SMPUMBIU_OFFSET) /* SMPU Master Bus Interface Unit Register
(32-bits) */
+#define R_SMPU_SMPUFBIU (R_SMPU_BASE +
R_SMPU_SMPUFBIU_OFFSET) /* SMPU Function Bus Interface Unit
Register (32-bits) */
+#define R_SMPU_SMPUSRAM0 (R_SMPU_BASE +
R_SMPU_SMPUSRAM0_OFFSET) /* SMPU SRAM Protection Register 0
(32-bits) */
+#define R_SMPU_SMPUPBIU(p) (R_SMPU_BASE +
R_SMPU_SMPUPBIU_OFFSET + (p)*0x0004) /* SMPU Peripheral Bus Interface Unit
Register (32-bits) */
+#define R_SPMON_MSPMPUOAD (R_SPMON_BASE +
R_SPMON_MSPMPUOAD_OFFSET) /* Secure Protection Monitor Master MPU
Override Address Register (32-bits) */
+#define R_SPMON_MSPMPUCTL (R_SPMON_BASE +
R_SPMON_MSPMPUCTL_OFFSET) /* Secure Protection Monitor Master MPU
Control Register (32-bits) */
+#define R_SPMON_MSPMPUPT (R_SPMON_BASE +
R_SPMON_MSPMPUPT_OFFSET) /* Secure Protection Monitor Master MPU
Protection Type Register (16-bits) */
+#define R_SPMON_MSPMPUSA (R_SPMON_BASE +
R_SPMON_MSPMPUSA_OFFSET) /* Secure Protection Monitor Master MPU
Start Address Register (32-bits) */
+#define R_SPMON_MSPMPUEA (R_SPMON_BASE +
R_SPMON_MSPMPUEA_OFFSET) /* Secure Protection Monitor Master MPU End
Address Register (32-bits) */
+#define R_SPMON_PSPMPUOAD (R_SPMON_BASE +
R_SPMON_PSPMPUOAD_OFFSET) /* Secure Protection Monitor Peripheral MPU
Override Address Register (32-bits) */
+#define R_SPMON_PSPMPUCTL (R_SPMON_BASE +
R_SPMON_PSPMPUCTL_OFFSET) /* Secure Protection Monitor Peripheral MPU
Control Register (32-bits) */
+#define R_SPMON_PSPMPUPT (R_SPMON_BASE +
R_SPMON_PSPMPUPT_OFFSET) /* Secure Protection Monitor Peripheral MPU
Protection Type Register (16-bits) */
+#define R_SPMON_PSPMPUSA (R_SPMON_BASE +
R_SPMON_PSPMPUSA_OFFSET) /* Secure Protection Monitor Peripheral MPU
Start Address Register (32-bits) */
+#define R_SPMON_PSPMPUEA (R_SPMON_BASE +
R_SPMON_PSPMPUEA_OFFSET) /* Secure Protection Monitor Peripheral MPU
End Address Register (32-bits) */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MMPU Control Register A (32-bits) */
+
+#define R_MMPU_MMPUCTLA_KEY (8 << 8) /* 100: Key Code These
bits are used to enable or disable writing of the OAD and ENABLE bit. */
+#define R_MMPU_MMPUCTLA_KEY_MASK (0xff)
+#define R_MMPU_MMPUCTLA_OAD (1 << 1) /* 02: Operation after
detection */
+#define R_MMPU_MMPUCTLA_ENABLE (1 << 0) /* 01: Master Group enable
*/
+#define R_MMPU_MMPUACA_SIZE 16
+
+/* MMPU Access Control Register A (32-bits) */
+
+#define R_MMPU_MMPUACA_WP (1 << 2) /* 04: Write protection */
+#define R_MMPU_MMPUACA_RP (1 << 1) /* 02: Read protection */
+#define R_MMPU_MMPUACA_ENABLE (1 << 0) /* 01: Region enable */
+#define R_MMPU_MMPUSA_SIZE 16
+
+/* MMPU Start Address Register A (32-bits) */
+
+#define R_MMPU_MMPUSA_MMPUSA (32 << 0) /* 01: Address where the
region starts, for use in region determination. NOTE: The low-order 2 bits are
fixed to 0. */
+#define R_MMPU_MMPUSA_MMPUSA_MASK (0xffffffff)
+#define R_MMPU_MMPUEA_SIZE 16
+
+/* MMPU End Address Register A (32-bits) */
+
+#define R_MMPU_MMPUEA_MMPUEA (32 << 0) /* 01: Region end address
register Address where the region end, for use in region determination. NOTE:
The low-order 2 bits are fixed to 1. */
+#define R_MMPU_MMPUEA_MMPUEA_MASK (0xffffffff)
+
+/* MMPU Protection Type Register A (16-bits) */
+
+#define R_MMPU_MMPUPTA_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_MMPU_MMPUPTA_KEY_MASK (0xff)
+#define R_MMPU_MMPUPTA_PROTECT (1 << 0) /* 01: Protection of
register (MMPUSAn, MMPUEAn and MMPUACAn) */
+
+/* SMPU Control Register (32-bits) */
+
+#define R_SMPU_SMPUCTL_KEY (8 << 8) /* 100: Key Code This bit
is used to enable or disable rewriting of the PROTECT and OAD bit. */
+#define R_SMPU_SMPUCTL_KEY_MASK (0xff)
+#define R_SMPU_SMPUCTL_PROTECT (1 << 1) /* 02: Protection of
register */
+#define R_SMPU_SMPUCTL_OAD (1 << 0) /* 01: Master Group enable
*/
+
+/* SMPU Master Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUMBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUMBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+
+/* SMPU Function Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUFBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUFBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUFBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUFBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* SMPU SRAM Protection Register 0 (32-bits) */
+
+#define R_SMPU_SMPUSRAM0_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUSRAM0_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUSRAM0_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUSRAM0_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+#define R_SMPU_SMPUPBIU_SIZE 3
+
+/* SMPU Peripheral Bus Interface Unit Register (32-bits) */
+
+#define R_SMPU_SMPUPBIU_WPGRPA (1 << 3) /* 08: Master Group A
Write protection */
+#define R_SMPU_SMPUPBIU_RPGRPA (1 << 2) /* 04: Master Group A Read
protection */
+#define R_SMPU_SMPUPBIU_WPCPU (1 << 1) /* 02: CPU Write
protection */
+#define R_SMPU_SMPUPBIU_RPCPU (1 << 0) /* 01: CPU Read protection
*/
+
+/* Secure Protection Monitor Master MPU Override Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUOAD_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUOAD_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUOAD_OAD (1 << 0) /* 01: Operation after
detection */
+
+/* Secure Protection Monitor Master MPU Control Register (32-bits) */
+
+#define R_SPMON_MSPMPUCTL_ERROR (1 << 8) /* 100: Stack Pointer
Monitor Error Flag */
+#define R_SPMON_MSPMPUCTL_ENABLE (1 << 0) /* 01: Stack Pointer
Monitor Enable */
+
+/* Secure Protection Monitor Master MPU Protection Type Register (16-bits) */
+
+#define R_SPMON_MSPMPUPT_KEY (8 << 8) /* 100: Write Keyword The
data written to these bits are not stored. */
+#define R_SPMON_MSPMPUPT_KEY_MASK (0xff)
+#define R_SPMON_MSPMPUPT_PROTECT (1 << 0) /* 01: Protection of
register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */
+
+/* Secure Protection Monitor Master MPU Start Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUSA_MSPMPUSA (32 << 0) /* 01: Region start
address register Address where the region starts, for use in region
determination. NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are
fixed to 0. */
+#define R_SPMON_MSPMPUSA_MSPMPUSA_MASK (0xffffffff)
+
+/* Secure Protection Monitor Master MPU End Address Register (32-bits) */
+
+#define R_SPMON_MSPMPUEA_MSPMPUEA (32 << 0) /* 01: Region end address
register Address where the region starts, for use in region determination.
NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1. */
+#define R_SPMON_MSPMPUEA_MSPMPUEA_MASK (0xffffffff)
Review Comment:
Ditto
##########
arch/arm/src/ra/hardware/ra_option_setting.h:
##########
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * arch/arm/src/ra/hardware/ra_option_setting.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+#define __ARCH_ARM_SRC_RA_HARDWARE_RA_OFS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "hardware/ra_memorymap.h"
+
+#if defined(CONFIG_RA4M1_FAMILY)
+# include "hardware/ra4m1_pinmap.h"
+#else
+# error "Unsupported RA memory map"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define R_OFS0_OFFSET 0x0000 /* Option Function Select Register 0
(32-bits) */
+#define R_OFS1_OFFSET 0x0004 /* Option Function Select Register 1
(32-bits) */
+
+/* Register Addresses *******************************************************/
+
+/* Option Function Select Registers */
+
+# define R_OFS0 (R_OFS_BASE + R_OFS0_OFFSET)
+# define R_OFS1 (R_OFS_BASE + R_OFS1_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Option Function Select Register 0 */
+
+#define R_OFS0_RESERVED_31 (1 << 31)
/* Bit 31: Reserved */
+#define R_OFS0_WDTSTPCTL (1 << 30)
/* Bit 30: WDT Stop Control */
+#define R_OFS0_RESERVED_29 (1 << 29)
/* Bit 29: Reserved */
+#define R_OFS0_WDTRSTIRQS (1 << 28)
/* Bit 28: WDT Reset Interrupt Request Select*/
+#define R_OFS0_WDTRPSS_SHIFT (26)
/* Bit 27-26: WDT Window Start Position Select*/
+#define R_OFS0_WDTRPSS_MASK (3 << R_OFS0_WDTRPSS_SHIFT)
+# define R_OFS0_WDTRPSS_25 (0 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 25% */
+# define R_OFS0_WDTRPSS_50 (1 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 50% */
+# define R_OFS0_WDTRPSS_75 (2 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 75% */
+# define R_OFS0_WDTRPSS_100 (3 << R_OFS0_WDTRPSS_SHIFT)
/* WDT Window Start Position Select 100% */
+#define R_OFS0_WDTRPES_SHIFT (24)
/* Bit 25-24: WDT Window End Position Select*/
+#define R_OFS0_WDTRPES_MASK (3 << R_OFS0_WDTRPES_SHIFT)
+# define R_OFS0_WDTRPES_75 (0 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 75% */
+# define R_OFS0_WDTRPES_50 (1 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 50% */
+# define R_OFS0_WDTRPES_25 (2 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 25% */
+# define R_OFS0_WDTRPES_0 (3 << R_OFS0_WDTRPES_SHIFT)
/* WDT Window End Position Select 0% */
+#define R_OFS0_WDTCKS_SHIFT (20)
/* Bit 23-20: WDT Clock Frequency Division Ratio Select*/
+#define R_OFS0_WDTCKS_MASK (0xF << R_OFS0_WDTCKS_SHIFT)
+# define R_OFS0_WDTCKS_DIV_4 (1 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 4 */
+# define R_OFS0_WDTCKS_DIV_64 (4 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 64 */
+# define R_OFS0_WDTCKS_DIV_128 (15 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 128 */
+# define R_OFS0_WDTCKS_DIV_512 (6 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 512 */
+# define R_OFS0_WDTCKS_DIV_2048 (7 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 2048 */
+# define R_OFS0_WDTCKS_DIV_8192 (8 << R_OFS0_WDTCKS_SHIFT)
/* PCLKB divided by 8192 */
+#define R_OFS0_WDTTOPS_SHIFT (18)
/* Bit 19-18: WDT Timeout Period Select */
+#define R_OFS0_WDTTOPS_MASK (3 << R_OFS0_WDTTOPS_SHIFT)
+# define R_OFS0_WDTTOPS_1024_CYCLES (0 << R_OFS0_WDTTOPS_SHIFT)
/* 1024 cycles */
+# define R_OFS0_WDTTOPS_4096_CYCLES (1 << R_OFS0_WDTTOPS_SHIFT)
/* 4096 cycles */
+# define R_OFS0_WDTTOPS_8192_CYCLES (2 << R_OFS0_WDTTOPS_SHIFT)
/* 8192 cycles */
+# define R_OFS0_WDTTOPS_16384_CYCLES (3 << R_OFS0_WDTTOPS_SHIFT)
/* 16384 cycles */
+#define R_OFS0_RESERVED_16_15_SHIFT (15)
/* Bit 16-15: Reserved */
+#define R_OFS0_RESERVED_16_15_MASK (3 << R_OFS0_RESERVED_16_15_SHIFT)
/* Bit 16-15: Reserved */
+#define R_OFS0_WDTSTRT (1 << 17)
/* Bit 17: WDT Start Mode Select */
+#define R_OFS0_IWDTSTPCTL (1 << 14)
/* Bit 14: IWDT Stop Control */
+#define R_OFS0_RESERVED_13 (1 << 13)
/* Bit 13: Reserved */
+#define R_OFS0_IWDTRSTIRQS (1 << 12)
/* Bit 12: IWDT Reset Interrupt Request Select */
+#define R_OFS0_IWDTRPSS_SHIFT (10)
/* Bit 11-10: IWDT Window Start Position Select */
+#define R_OFS0_IWDTRPSS_MASK (3 << R_OFS0_IWDTRPSS_SHIFT)
+# define R_OFS0_IWDTRPSS_25 (0 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 25% */
+# define R_OFS0_IWDTRPSS_50 (1 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 50% */
+# define R_OFS0_IWDTRPSS_75 (2 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 75% */
+# define R_OFS0_IWDTRPSS_100 (3 << R_OFS0_IWDTRPSS_SHIFT)
/* IWDT Window Start Position Select 100% */
+#define R_OFS0_IWDTRPES_SHIFT (8)
/* Bit 9-8: IWDT Window End Position Select*/
+#define R_OFS0_IWDTRPES_MASK (3 << R_OFS0_IWDTRPES_SHIFT)
+# define R_OFS0_IWDTRPES_75 (0 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 75% */
+# define R_OFS0_IWDTRPES_50 (1 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 50% */
+# define R_OFS0_IWDTRPES_25 (2 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 25% */
+# define R_OFS0_IWDTRPES_0 (3 << R_OFS0_IWDTRPES_SHIFT)
/* IWDT Window End Position Select 0% */
+#define R_OFS0_IWDTCKS_SHIFT (4)
/* Bit 7-4: IWDT Clock Frequency Division Ratio Select*/
+#define R_OFS0_IWDTCKS_MASK (0xF << R_OFS0_IWDTCKS_SHIFT)
+# define R_OFS0_IWDTCKS_DIV_1 (0 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 1 */
+# define R_OFS0_IWDTCKS_DIV_16 (2 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 16 */
+# define R_OFS0_IWDTCKS_DIV_32 (3 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 32 */
+# define R_OFS0_IWDTCKS_DIV_64 (4 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 64 */
+# define R_OFS0_IWDTCKS_DIV_128 (15 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 128 */
+# define R_OFS0_IWDTCKS_DIV_256 (5 << R_OFS0_IWDTCKS_SHIFT)
/* Divided by 256 */
+#define R_OFS0_IWDTTOPS_SHIFT (2)
/* Bit 3-2: IWDT Timeout Period Select */
+#define R_OFS0_IWDTTOPS_MASK (3 << R_OFS0_IWDTTOPS_SHIFT)
+# define R_OFS0_IWDTTOPS_128_CYCLES (0 << R_OFS0_IWDTTOPS_SHIFT)
/* 128 cycles */
+# define R_OFS0_IWDTTOPS_512_CYCLES (1 << R_OFS0_IWDTTOPS_SHIFT)
/* 512 cycles */
+# define R_OFS0_IWDTTOPS_1024_CYCLES (2 << R_OFS0_IWDTTOPS_SHIFT)
/* 1024 cycles */
+# define R_OFS0_IWDTTOPS_2048_CYCLES (3 << R_OFS0_IWDTTOPS_SHIFT)
/* 2048 cycles */
+#define R_OFS0_IWDTSTRT (1 << 1)
/* Bit 1: IWDT Start Mode Select */
+#define R_OFS0_RESERVED_0 (1 << 0)
/* Bit 0: Reserved */
+
+/* Option Function Select Register 1 */
+
+#define R_OFS1_RESERVED_31_15_SHIFT (15) /* Bit
31-15: Reserved */
+#define R_OFS1_RESERVED_16_15_MASK (0x1FFFF <<
R_OFS1_RESERVED_31_15_SHIFT)
+#define R_OFS1_HOCOFRQ1_SHIFT (12) /* Bit
14-12: IWDT Timeout Period Select */
+#define R_OFS1_HOCOFRQ1_MASK (7 << R_OFS1_HOCOFRQ1_SHIFT)
+# define R_OFS1_HOCOFRQ1_24MHZ (0 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO
24 Mhz */
+# define R_OFS1_HOCOFRQ1_32MHZ (2 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO
32 Mhz */
+# define R_OFS1_HOCOFRQ1_48MHZ (4 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO
48 Mhz */
+# define R_OFS1_HOCOFRQ1_64MHZ (5 << R_OFS1_HOCOFRQ1_SHIFT) /* HOCO
64 Mhz */
+#define R_OFS1_RESERVED_11_9_SHIFT (9) /* Bit
11-9: Reserved */
+#define R_OFS1_RESERVED_11_9_MASK (7 << R_OFS1_RESERVED_11_9_SHIFT)
+#define R_OFS1_HOCOEN (1 << 8) /* Bit 8:
HOCO Oscillation Enable */
+#define R_OFS1_RESERVED_7_6_SHIFT (6) /* Bit
7-6: Reserved */
+#define R_OFS1_RESERVED_7_6_MASK (3 << R_OFS1_RESERVED_7_6_SHIFT)
+#define R_OFS1_VDSEL1_SHIFT (3) /* Bit
5-3: Voltage Detection 0 Level Select */
+#define R_OFS1_VDSEL1_MASK (7 << R_OFS1_VDSEL1_SHIFT)
+# define R_OFS1_VDSEL1_3_84V (0 << R_OFS1_VDSEL1_SHIFT) /*
Selects 3.84 V */
+# define R_OFS1_VDSEL1_2_82V (1 << R_OFS1_VDSEL1_SHIFT) /*
Selects 2.82 V*/
+# define R_OFS1_VDSEL1_2_51V (2 << R_OFS1_VDSEL1_SHIFT) /*
Selects 2.51 V */
+# define R_OFS1_VDSEL1_1_90V (3 << R_OFS1_VDSEL1_SHIFT) /*
Selects 1.70 V */
+# define R_OFS1_VDSEL1_1_70V (4 << R_OFS1_VDSEL1_SHIFT) /*
Selects 1.70 V */
+#define R_OFS1_LVDAS (1 << 2) /* Bit 8:
Voltage Detection 0 Circuit Start*/
+#define R_OFS1_RESERVED_1_0_SHIFT (0) /* Bit
1-0: Reserved */
+#define R_OFS1_RESERVED_1_0_MASK (3 << R_OFS1_RESERVED_1_0_SHIFT)
Review Comment:
Align
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