On Tue, 14 Jul 2020 at 06:20, Saku Ytti <[email protected]> wrote: > > On Mon, 13 Jul 2020 at 20:39, James Bensley > <[email protected]> wrote: > > > Back in the 7600s it was NPU based, and what we call NPUs today are > > sometimes a collection of ASICs that form a "complex of ASICs". That > > is what powered the 7600, the NP3C NPU. 7600s used a group of ASICs > > working together to perform forwarding lookups, buffering, backplane > > sending/receiving etc. > > NP3C was on ES20+ (not ES20). The ASR9k Trident was the same EZchip > NP3C. But of course the vast majority of 7600 linecards were PFC3, > clearly not a NPU.
You're right, and I should have been clearer that the ES20+ cards used the NP3C NPU. But I wouldn't say that ES20 cards / PFC3 cards clearly are not an NPU. I think they are actually in the interesting middle ground between what I would call an ASIC powered device and an NPU powered device. Take the ME3600X and early ASR920 devices for example (I don't know so much about the more recent ASR920s); these are single chip all-in-one ASIC boxes. Technically the ME3600X/ME3800X use two ASICs linked via a PCI link which is non-blocking, but this is just horizontal scaling to accomodate for additional ports, it's two of the exact same ASIC which both have on chip TCAM and buffers and both carry all forwarding information and perform all functions. So in these two pizza boxes, we have a single ASIC that does everything; the front panel ports connect to the ASICs, they perform ingress queueing, forwarding look-ups, egress re-writes, egress queueing, everything. The PFC3 cards on 7600 require a collection of ASICs (one to connect to the front panel ports, one for queueing, one for forwarding lookups and rewrites, one for backplane / crossbar transmission and reception etc.), so whilst they probably don't fit a strict definition of NPU I think they are in the interest in-between stage of evolving from single ASIC -> a bunch of loosely coupled ASICs -> a complex of tightly bound ASIC. Cheers, James. _______________________________________________ cisco-nsp mailing list [email protected] https://puck.nether.net/mailman/listinfo/cisco-nsp archive at http://puck.nether.net/pipermail/cisco-nsp/
