yvvan created this revision.
yvvan added reviewers: bkramer, klimek.
Herald added subscribers: JDevlieghere, nhaehnle, arsenm.
Herald added a reviewer: deadalnix.
I've tested it on Windows with 64-bit icl
These are mostly workarounds for
https://software.intel.com/en-us/comment/1919743 ,
https://software.intel.com/en-us/forums/intel-c-compiler/topic/749369 and few
more enum-related issues
https://reviews.llvm.org/D44426
Files:
include/llvm-c/Target.h
include/llvm/ADT/BitmaskEnum.h
include/llvm/Analysis/AliasAnalysis.h
lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
lib/Target/AMDGPU/SIISelLowering.cpp
tools/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h
tools/llvm-nm/llvm-nm.cpp
Index: tools/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h
===================================================================
--- tools/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h
+++ tools/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h
@@ -282,8 +282,12 @@
/// SExpr objects cannot be deleted.
// This declaration is public to workaround a gcc bug that breaks building
- // with REQUIRES_EH=1.
+ // with REQUIRES_EH=1. Do not mark it 'delete' to avoid error with intel compiler.
+#ifdef __INTEL_COMPILER
+ void operator delete(void *);
+#else
void operator delete(void *) = delete;
+#endif
/// Returns the instruction ID for this expression.
/// All basic block instructions have a unique ID (i.e. virtual register).
Index: tools/llvm-nm/llvm-nm.cpp
===================================================================
--- tools/llvm-nm/llvm-nm.cpp
+++ tools/llvm-nm/llvm-nm.cpp
@@ -876,14 +876,14 @@
case ELF::SHT_PROGBITS:
case ELF::SHT_DYNAMIC:
switch (SecI->getFlags()) {
- case (ELF::SHF_ALLOC | ELF::SHF_EXECINSTR):
+ case (ELF::SHF_ALLOC | static_cast<int>(ELF::SHF_EXECINSTR)):
return 't';
- case (ELF::SHF_TLS | ELF::SHF_ALLOC | ELF::SHF_WRITE):
- case (ELF::SHF_ALLOC | ELF::SHF_WRITE):
+ case (ELF::SHF_TLS | static_cast<int>(ELF::SHF_ALLOC) | static_cast<int>(ELF::SHF_WRITE)):
+ case (ELF::SHF_ALLOC | static_cast<int>(ELF::SHF_WRITE)):
return 'd';
case ELF::SHF_ALLOC:
- case (ELF::SHF_ALLOC | ELF::SHF_MERGE):
- case (ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::SHF_STRINGS):
+ case (ELF::SHF_ALLOC | static_cast<int>(ELF::SHF_MERGE)):
+ case (ELF::SHF_ALLOC | static_cast<int>(ELF::SHF_MERGE) | static_cast<int>(ELF::SHF_STRINGS)):
return 'r';
}
break;
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -6128,11 +6128,13 @@
SIInstrFlags::P_SUBNORMAL |
SIInstrFlags::P_NORMAL;
+#ifndef __INTEL_COMPILER
static_assert(((~(SIInstrFlags::S_NAN |
SIInstrFlags::Q_NAN |
SIInstrFlags::N_INFINITY |
SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
"mask not equal");
+#endif
SDLoc DL(N);
return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
Index: lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
===================================================================
--- lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
+++ lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp
@@ -76,24 +76,24 @@
return "sdata4";
case dwarf::DW_EH_PE_sdata8:
return "sdata8";
- case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4:
+ case dwarf::DW_EH_PE_pcrel | static_cast<int>(dwarf::DW_EH_PE_udata4):
return "pcrel udata4";
- case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4:
+ case dwarf::DW_EH_PE_pcrel | static_cast<int>(dwarf::DW_EH_PE_sdata4):
return "pcrel sdata4";
- case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8:
+ case dwarf::DW_EH_PE_pcrel | static_cast<int>(dwarf::DW_EH_PE_udata8):
return "pcrel udata8";
- case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8:
+ case dwarf::DW_EH_PE_pcrel | static_cast<int>(dwarf::DW_EH_PE_sdata8):
return "pcrel sdata8";
- case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4
+ case dwarf::DW_EH_PE_indirect | static_cast<int>(dwarf::DW_EH_PE_pcrel) | static_cast<int>(dwarf::DW_EH_PE_udata4)
:
return "indirect pcrel udata4";
- case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
+ case dwarf::DW_EH_PE_indirect | static_cast<int>(dwarf::DW_EH_PE_pcrel) | static_cast<int>(dwarf::DW_EH_PE_sdata4)
:
return "indirect pcrel sdata4";
- case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8
+ case dwarf::DW_EH_PE_indirect | static_cast<int>(dwarf::DW_EH_PE_pcrel) | static_cast<int>(dwarf::DW_EH_PE_udata8)
:
return "indirect pcrel udata8";
- case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8
+ case dwarf::DW_EH_PE_indirect | static_cast<int>(dwarf::DW_EH_PE_pcrel) | static_cast<int>(dwarf::DW_EH_PE_sdata8)
:
return "indirect pcrel sdata8";
}
Index: include/llvm/Analysis/AliasAnalysis.h
===================================================================
--- include/llvm/Analysis/AliasAnalysis.h
+++ include/llvm/Analysis/AliasAnalysis.h
@@ -251,7 +251,7 @@
/// This property corresponds to the LLVM IR
/// inaccessiblemem_or_argmemonly attribute.
FMRB_OnlyAccessesInaccessibleOrArgMem = FMRL_InaccessibleMem |
- FMRL_ArgumentPointees |
+ static_cast<int>(FMRL_ArgumentPointees) |
static_cast<int>(ModRefInfo::ModRef),
/// This function does not perform any non-local stores or volatile loads,
Index: include/llvm/ADT/BitmaskEnum.h
===================================================================
--- include/llvm/ADT/BitmaskEnum.h
+++ include/llvm/ADT/BitmaskEnum.h
@@ -70,6 +70,11 @@
template <typename E, typename Enable = void>
struct is_bitmask_enum : std::false_type {};
+#ifdef __INTEL_COMPILER
+template <typename E>
+struct is_bitmask_enum<E, typename std::enable_if<std::is_enum<E>::value>::type> : std::true_type {};
+#endif
+
template <typename E>
struct is_bitmask_enum<
E, typename std::enable_if<sizeof(E::LLVM_BITMASK_LARGEST_ENUMERATOR) >=
@@ -78,6 +83,7 @@
/// Get a bitmask with 1s in all places up to the high-order bit of E's largest
/// value.
+#ifndef __INTEL_COMPILER
template <typename E> typename std::underlying_type<E>::type Mask() {
// On overflow, NextPowerOf2 returns zero with the type uint64_t, so
// subtracting 1 gives us the mask with all bits set, like we want.
@@ -85,6 +91,11 @@
E::LLVM_BITMASK_LARGEST_ENUMERATOR)) -
1;
}
+#else
+template <typename E> typename std::underlying_type<E>::type Mask() {
+ return std::numeric_limits<std::underlying_type<E>::type>::max();
+}
+#endif
/// Check that Val is in range for E, and return Val cast to E's underlying
/// type.
Index: include/llvm-c/Target.h
===================================================================
--- include/llvm-c/Target.h
+++ include/llvm-c/Target.h
@@ -22,7 +22,7 @@
#include "llvm-c/Types.h"
#include "llvm/Config/llvm-config.h"
-#if defined(_MSC_VER) && !defined(inline)
+#if defined(_MSC_VER) && !defined(inline) && !defined(__INTEL_COMPILER)
#define inline __inline
#endif
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