================
@@ -108,935 +108,1006 @@ def TTAscalonXModel : SchedMachineModel {
HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
HasStdExtZkr];
-}
-
-let SchedModel = TTAscalonXModel in {
-//===----------------------------------------------------------------------===//
-// Define each kind of processor resource and number available.
-
-let BufferSize = 16 in {
- def AscalonLS : ProcResource<3>;
- def AscalonFXA : ProcResource<1>; // ALU, FP/VEC -> INT, MUL, DIV, CSR
- def AscalonFXB : ProcResource<1>; // ALU, INT -> FP/VEC
- def AscalonFXC : ProcResource<2>; // ALU, BR
- def AscalonFXD : ProcResource<2>; // ALU
- def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC,
AscalonFXD]>;
- // FP
- def AscalonFPA : ProcResource<1>; // Pipe A also handles FP/VEC -> INT
- def AscalonFPB : ProcResource<1>;
- def AscalonFP : ProcResGroup<[AscalonFPA, AscalonFPB]>;
- // Vector
- def AscalonVA : ProcResource<1>;
- def AscalonVB : ProcResource<1>;
- def AscalonV : ProcResGroup<[AscalonVA, AscalonVB]>;
+ string Name;
+ bit HasReducedFP64VectorThroughput;
}
+def TTAscalonXModel : TTAscalonSchedMachineModel {
+ // TODO: This should technically be AscalonX.
+ let Name = "Ascalon";
+ let HasReducedFP64VectorThroughput = false;
+}
-//===----------------------------------------------------------------------===//
+def TTAscalonXGModel : TTAscalonSchedMachineModel {
+ let Name = "AscalonXG";
+ let HasReducedFP64VectorThroughput = true;
+}
-// Branching
-def : WriteRes<WriteJmp, [AscalonFXC]>;
-def : WriteRes<WriteJal, [AscalonFXC]>;
-def : WriteRes<WriteJalr, [AscalonFXC]>;
-
-// Integer arithmetic and logic
-def : WriteRes<WriteIALU32, [AscalonFX]>;
-def : WriteRes<WriteIALU, [AscalonFX]>;
-def : WriteRes<WriteShiftImm32, [AscalonFX]>;
-def : WriteRes<WriteShiftImm, [AscalonFX]>;
-def : WriteRes<WriteShiftReg32, [AscalonFX]>;
-def : WriteRes<WriteShiftReg, [AscalonFX]>;
-
-// Integer multiplication
-let Latency = 3 in {
-def : WriteRes<WriteIMul, [AscalonFXA]>;
-def : WriteRes<WriteIMul32, [AscalonFXA]>;
+/// Latency and occupancy of the extra FP64 vector unit on Ascalon XG for
+/// vector instructions producing FP64 results.
+class AscalonXGFP64Vec<int Cycles> {
+ int Latency = !add(Cycles, 8);
+ int ReleaseAtCycles = !mul(Cycles, 4);
}
-// Integer division
-// Worst case latency is used.
+multiclass TTAscalonSchedResources<bit ReducedFP64Vec> {
+
//===--------------------------------------------------------------------===//
+ // Define each kind of processor resource and number available.
+ let BufferSize = 16 in {
+ def LS : ProcResource<3>;
+ def FXA : ProcResource<1>; // ALU, FP/VEC -> INT, MUL, DIV, CSR
+ def FXB : ProcResource<1>; // ALU, INT -> FP/VEC
+ def FXC : ProcResource<2>; // ALU, BR
+ def FXD : ProcResource<2>; // ALU
+ def FX : ProcResGroup<[!cast<ProcResource>(NAME # "FXA"),
+ !cast<ProcResource>(NAME # "FXB"),
+ !cast<ProcResource>(NAME # "FXC"),
+ !cast<ProcResource>(NAME # "FXD")]>;
+ // FP
+ def FPA : ProcResource<1>; // Pipe A also handles FP/VEC -> INT
+ def FPB : ProcResource<1>;
+ def FP : ProcResGroup<[!cast<ProcResource>(NAME # "FPA"),
+ !cast<ProcResource>(NAME # "FPB")]>;
+ // Vector
+ def VA : ProcResource<1>;
+ def VB : ProcResource<1>;
+ def V : ProcResGroup<[!cast<ProcResource>(NAME # "VA"),
+ !cast<ProcResource>(NAME # "VB")]>;
+ // Extra unit that models the reduced throughput of vector instructions
+ // producing FP64 results.
+ if ReducedFP64Vec then
+ def FP64V : ProcResource<2>;
+ }
-let Latency = 7, ReleaseAtCycles = [7] in {
- def : WriteRes<WriteIDiv32, [AscalonFXA]>;
- def : WriteRes<WriteIDiv, [AscalonFXA]>;
- def : WriteRes<WriteIRem32, [AscalonFXA]>;
- def : WriteRes<WriteIRem, [AscalonFXA]>;
-}
+ defvar AscalonLS = !cast<ProcResource>(NAME # "LS");
+ defvar AscalonFXA = !cast<ProcResource>(NAME # "FXA");
+ defvar AscalonFXB = !cast<ProcResource>(NAME # "FXB");
+ defvar AscalonFXC = !cast<ProcResource>(NAME # "FXC");
+ defvar AscalonFXD = !cast<ProcResource>(NAME # "FXD");
+ defvar AscalonFX = !cast<ProcResGroup>(NAME # "FX");
+ defvar AscalonFPA = !cast<ProcResource>(NAME # "FPA");
+ defvar AscalonFPB = !cast<ProcResource>(NAME # "FPB");
+ defvar AscalonFP = !cast<ProcResGroup>(NAME # "FP");
+ defvar AscalonVA = !cast<ProcResource>(NAME # "VA");
+ defvar AscalonVB = !cast<ProcResource>(NAME # "VB");
+ defvar AscalonV = !cast<ProcResGroup>(NAME # "V");
+
+ // Only used when ReducedFP64Vec is set; fall back to the vector pipes
+ // otherwise so that the defvar is always well-formed.
+ defvar AscalonFP64V = !if(ReducedFP64Vec,
+ !cast<ProcResource>(NAME # "FP64V"), AscalonV);
+
+
//===--------------------------------------------------------------------===//
+ // Branching
+ def : WriteRes<WriteJmp, [AscalonFXC]>;
+ def : WriteRes<WriteJal, [AscalonFXC]>;
+ def : WriteRes<WriteJalr, [AscalonFXC]>;
+
+ // Integer arithmetic and logic
+ def : WriteRes<WriteIALU32, [AscalonFX]>;
+ def : WriteRes<WriteIALU, [AscalonFX]>;
+ def : WriteRes<WriteShiftImm32, [AscalonFX]>;
+ def : WriteRes<WriteShiftImm, [AscalonFX]>;
+ def : WriteRes<WriteShiftReg32, [AscalonFX]>;
+ def : WriteRes<WriteShiftReg, [AscalonFX]>;
+
+ // Integer multiplication
+ let Latency = 3 in {
+ def : WriteRes<WriteIMul, [AscalonFXA]>;
+ def : WriteRes<WriteIMul32, [AscalonFXA]>;
+ }
-// Bitmanip
-def : WriteRes<WriteRotateImm, [AscalonFX]>;
-def : WriteRes<WriteRotateImm32, [AscalonFX]>;
-def : WriteRes<WriteRotateReg, [AscalonFX]>;
-def : WriteRes<WriteRotateReg32, [AscalonFX]>;
-
-def : WriteRes<WriteCLZ, [AscalonFX]>;
-def : WriteRes<WriteCLZ32, [AscalonFX]>;
-def : WriteRes<WriteCTZ, [AscalonFX]>;
-def : WriteRes<WriteCTZ32, [AscalonFX]>;
-
-def : WriteRes<WriteCPOP, [AscalonFX]>;
-def : WriteRes<WriteCPOP32, [AscalonFX]>;
-
-def : WriteRes<WriteORCB, [AscalonFX]>;
-
-def : WriteRes<WriteIMinMax, [AscalonFX]>;
-
-def : WriteRes<WriteREV8, [AscalonFX]>;
-
-def : WriteRes<WriteSHXADD, [AscalonFX]>;
-def : WriteRes<WriteSHXADD32, [AscalonFX]>;
-
-// Single-bit instructions
-def : WriteRes<WriteSingleBit, [AscalonFX]>;
-def : WriteRes<WriteSingleBitImm, [AscalonFX]>;
-def : WriteRes<WriteBEXT, [AscalonFX]>;
-def : WriteRes<WriteBEXTI, [AscalonFX]>;
-
-// Memory
-def : WriteRes<WriteSTB, [AscalonLS]>;
-def : WriteRes<WriteSTH, [AscalonLS]>;
-def : WriteRes<WriteSTW, [AscalonLS]>;
-def : WriteRes<WriteSTD, [AscalonLS]>;
-def : WriteRes<WriteFST16, [AscalonLS]>;
-def : WriteRes<WriteFST32, [AscalonLS]>;
-def : WriteRes<WriteFST64, [AscalonLS]>;
-
-let Latency = 4 in {
-def : WriteRes<WriteLDB, [AscalonLS]>;
-def : WriteRes<WriteLDH, [AscalonLS]>;
-def : WriteRes<WriteLDW, [AscalonLS]>;
-def : WriteRes<WriteLDD, [AscalonLS]>;
-def : WriteRes<WriteFLD16, [AscalonLS]>;
-def : WriteRes<WriteFLD32, [AscalonLS]>;
-def : WriteRes<WriteFLD64, [AscalonLS]>;
-}
+ // Integer division
+ // Worst case latency is used.
-// Atomic memory
-def : WriteRes<WriteAtomicSTW, [AscalonLS]>;
-def : WriteRes<WriteAtomicSTD, [AscalonLS]>;
+ let Latency = 7, ReleaseAtCycles = [7] in {
+ def : WriteRes<WriteIDiv32, [AscalonFXA]>;
+ def : WriteRes<WriteIDiv, [AscalonFXA]>;
+ def : WriteRes<WriteIRem32, [AscalonFXA]>;
+ def : WriteRes<WriteIRem, [AscalonFXA]>;
+ }
-let Latency = 4 in {
-def : WriteRes<WriteAtomicW, [AscalonLS]>;
-def : WriteRes<WriteAtomicD, [AscalonLS]>;
-def : WriteRes<WriteAtomicLDW, [AscalonLS]>;
-def : WriteRes<WriteAtomicLDD, [AscalonLS]>;
-}
+ // Bitmanip
+ def : WriteRes<WriteRotateImm, [AscalonFX]>;
+ def : WriteRes<WriteRotateImm32, [AscalonFX]>;
+ def : WriteRes<WriteRotateReg, [AscalonFX]>;
+ def : WriteRes<WriteRotateReg32, [AscalonFX]>;
+
+ def : WriteRes<WriteCLZ, [AscalonFX]>;
+ def : WriteRes<WriteCLZ32, [AscalonFX]>;
+ def : WriteRes<WriteCTZ, [AscalonFX]>;
+ def : WriteRes<WriteCTZ32, [AscalonFX]>;
+
+ def : WriteRes<WriteCPOP, [AscalonFX]>;
+ def : WriteRes<WriteCPOP32, [AscalonFX]>;
+
+ def : WriteRes<WriteORCB, [AscalonFX]>;
+
+ def : WriteRes<WriteIMinMax, [AscalonFX]>;
+
+ def : WriteRes<WriteREV8, [AscalonFX]>;
+
+ def : WriteRes<WriteSHXADD, [AscalonFX]>;
+ def : WriteRes<WriteSHXADD32, [AscalonFX]>;
+
+ // Single-bit instructions
+ def : WriteRes<WriteSingleBit, [AscalonFX]>;
+ def : WriteRes<WriteSingleBitImm, [AscalonFX]>;
+ def : WriteRes<WriteBEXT, [AscalonFX]>;
+ def : WriteRes<WriteBEXTI, [AscalonFX]>;
+
+ // Memory
+ def : WriteRes<WriteSTB, [AscalonLS]>;
+ def : WriteRes<WriteSTH, [AscalonLS]>;
+ def : WriteRes<WriteSTW, [AscalonLS]>;
+ def : WriteRes<WriteSTD, [AscalonLS]>;
+ def : WriteRes<WriteFST16, [AscalonLS]>;
+ def : WriteRes<WriteFST32, [AscalonLS]>;
+ def : WriteRes<WriteFST64, [AscalonLS]>;
+
+ let Latency = 4 in {
+ def : WriteRes<WriteLDB, [AscalonLS]>;
+ def : WriteRes<WriteLDH, [AscalonLS]>;
+ def : WriteRes<WriteLDW, [AscalonLS]>;
+ def : WriteRes<WriteLDD, [AscalonLS]>;
+ def : WriteRes<WriteFLD16, [AscalonLS]>;
+ def : WriteRes<WriteFLD32, [AscalonLS]>;
+ def : WriteRes<WriteFLD64, [AscalonLS]>;
+ }
-// Half precision.
-let Latency = 3 in {
-def : WriteRes<WriteFAdd16, [AscalonFP]>;
-def : WriteRes<WriteFMul16, [AscalonFP]>;
-def : WriteRes<WriteFMA16, [AscalonFP]>;
-def : WriteRes<WriteFSGNJ16, [AscalonFP]>;
-def : WriteRes<WriteFMinMax16, [AscalonFP]>;
-}
+ // Atomic memory
+ def : WriteRes<WriteAtomicSTW, [AscalonLS]>;
+ def : WriteRes<WriteAtomicSTD, [AscalonLS]>;
-let Latency = 7, ReleaseAtCycles = [7] in {
-def : WriteRes<WriteFDiv16, [AscalonFP]>;
-def : WriteRes<WriteFSqrt16, [AscalonFP]>;
-}
+ let Latency = 4 in {
+ def : WriteRes<WriteAtomicW, [AscalonLS]>;
+ def : WriteRes<WriteAtomicD, [AscalonLS]>;
+ def : WriteRes<WriteAtomicLDW, [AscalonLS]>;
+ def : WriteRes<WriteAtomicLDD, [AscalonLS]>;
+ }
-// Single precision.
-let Latency = 3 in {
-def : WriteRes<WriteFAdd32, [AscalonFP]>;
-def : WriteRes<WriteFMul32, [AscalonFP]>;
-def : WriteRes<WriteFMA32, [AscalonFP]>;
-def : WriteRes<WriteFSGNJ32, [AscalonFP]>;
-def : WriteRes<WriteFMinMax32, [AscalonFP]>;
-}
+ // Half precision.
+ let Latency = 3 in {
+ def : WriteRes<WriteFAdd16, [AscalonFP]>;
+ def : WriteRes<WriteFMul16, [AscalonFP]>;
+ def : WriteRes<WriteFMA16, [AscalonFP]>;
+ def : WriteRes<WriteFSGNJ16, [AscalonFP]>;
+ def : WriteRes<WriteFMinMax16, [AscalonFP]>;
+ }
-let Latency = 7, ReleaseAtCycles = [7] in {
-def : WriteRes<WriteFDiv32, [AscalonFP]>;
-def : WriteRes<WriteFSqrt32, [AscalonFP]>;
-}
+ let Latency = 7, ReleaseAtCycles = [7] in {
+ def : WriteRes<WriteFDiv16, [AscalonFP]>;
+ def : WriteRes<WriteFSqrt16, [AscalonFP]>;
+ }
-// Double precision
-let Latency = 3 in {
-def : WriteRes<WriteFAdd64, [AscalonFP]>;
-def : WriteRes<WriteFMul64, [AscalonFP]>;
-def : WriteRes<WriteFMA64, [AscalonFP]>;
-def : WriteRes<WriteFSGNJ64, [AscalonFP]>;
-def : WriteRes<WriteFMinMax64, [AscalonFP]>;
-}
+ // Single precision.
+ let Latency = 3 in {
+ def : WriteRes<WriteFAdd32, [AscalonFP]>;
+ def : WriteRes<WriteFMul32, [AscalonFP]>;
+ def : WriteRes<WriteFMA32, [AscalonFP]>;
+ def : WriteRes<WriteFSGNJ32, [AscalonFP]>;
+ def : WriteRes<WriteFMinMax32, [AscalonFP]>;
+ }
-let Latency = 12, ReleaseAtCycles = [12] in {
-def : WriteRes<WriteFDiv64, [AscalonFP]>;
-def : WriteRes<WriteFSqrt64, [AscalonFP]>;
-}
+ let Latency = 7, ReleaseAtCycles = [7] in {
+ def : WriteRes<WriteFDiv32, [AscalonFP]>;
+ def : WriteRes<WriteFSqrt32, [AscalonFP]>;
+ }
-// Conversions
-def : WriteRes<WriteFCvtI32ToF16, [AscalonFXB]>;
-def : WriteRes<WriteFCvtI32ToF32, [AscalonFXB]>;
-def : WriteRes<WriteFCvtI32ToF64, [AscalonFXB]>;
-def : WriteRes<WriteFCvtI64ToF16, [AscalonFXB]>;
-def : WriteRes<WriteFCvtI64ToF32, [AscalonFXB]>;
-def : WriteRes<WriteFCvtI64ToF64, [AscalonFXB]>;
-def : WriteRes<WriteFCvtF16ToI32, [AscalonFXA]>;
-def : WriteRes<WriteFCvtF16ToI64, [AscalonFXA]>;
-def : WriteRes<WriteFCvtF16ToF32, [AscalonFP]>;
-def : WriteRes<WriteFCvtF16ToF64, [AscalonFP]>;
-def : WriteRes<WriteFCvtF32ToI32, [AscalonFXA]>;
-def : WriteRes<WriteFCvtF32ToI64, [AscalonFXA]>;
-def : WriteRes<WriteFCvtF32ToF16, [AscalonFP]>;
-def : WriteRes<WriteFCvtF32ToF64, [AscalonFP]>;
-def : WriteRes<WriteFCvtF64ToI32, [AscalonFXA]>;
-def : WriteRes<WriteFCvtF64ToI64, [AscalonFXA]>;
-def : WriteRes<WriteFCvtF64ToF16, [AscalonFP]>;
-def : WriteRes<WriteFCvtF64ToF32, [AscalonFP]>;
-
-def : WriteRes<WriteFClass16, [AscalonFP]>;
-def : WriteRes<WriteFClass32, [AscalonFP]>;
-def : WriteRes<WriteFClass64, [AscalonFP]>;
-def : WriteRes<WriteFCmp16, [AscalonFP]>;
-def : WriteRes<WriteFCmp32, [AscalonFP]>;
-def : WriteRes<WriteFCmp64, [AscalonFP]>;
-
-def : WriteRes<WriteFMovI16ToF16, [AscalonFXB]>;
-def : WriteRes<WriteFMovF16ToI16, [AscalonFXA]>;
-def : WriteRes<WriteFMovI32ToF32, [AscalonFXB]>;
-def : WriteRes<WriteFMovF32ToI32, [AscalonFXA]>;
-def : WriteRes<WriteFMovI64ToF64, [AscalonFXB]>;
-def : WriteRes<WriteFMovF64ToI64, [AscalonFXA]>;
-
-// Others
-def : WriteRes<WriteCSR, [AscalonFXA]>;
-def : WriteRes<WriteNop, [AscalonFX]>;
-
-def : InstRW<[WriteIALU], (instrs COPY)>;
+ // Double precision
+ let Latency = 3 in {
+ def : WriteRes<WriteFAdd64, [AscalonFP]>;
+ def : WriteRes<WriteFMul64, [AscalonFP]>;
+ def : WriteRes<WriteFMA64, [AscalonFP]>;
+ def : WriteRes<WriteFSGNJ64, [AscalonFP]>;
+ def : WriteRes<WriteFMinMax64, [AscalonFP]>;
+ }
-//===----------------------------------------------------------------------===//
-// Bypass and advance
-def : ReadAdvance<ReadJmp, 0>;
-def : ReadAdvance<ReadJalr, 0>;
-def : ReadAdvance<ReadCSR, 0>;
-def : ReadAdvance<ReadStoreData, 0>;
-def : ReadAdvance<ReadMemBase, 0>;
-def : ReadAdvance<ReadIALU, 0>;
-def : ReadAdvance<ReadIALU32, 0>;
-def : ReadAdvance<ReadShiftImm, 0>;
-def : ReadAdvance<ReadShiftImm32, 0>;
-def : ReadAdvance<ReadShiftReg, 0>;
-def : ReadAdvance<ReadShiftReg32, 0>;
-def : ReadAdvance<ReadIDiv, 0>;
-def : ReadAdvance<ReadIDiv32, 0>;
-def : ReadAdvance<ReadIRem, 0>;
-def : ReadAdvance<ReadIRem32, 0>;
-def : ReadAdvance<ReadIMul, 0>;
-def : ReadAdvance<ReadIMul32, 0>;
-def : ReadAdvance<ReadAtomicWA, 0>;
-def : ReadAdvance<ReadAtomicWD, 0>;
-def : ReadAdvance<ReadAtomicDA, 0>;
-def : ReadAdvance<ReadAtomicDD, 0>;
-def : ReadAdvance<ReadAtomicLDW, 0>;
-def : ReadAdvance<ReadAtomicLDD, 0>;
-def : ReadAdvance<ReadAtomicSTW, 0>;
-def : ReadAdvance<ReadAtomicSTD, 0>;
-def : ReadAdvance<ReadFStoreData, 0>;
-def : ReadAdvance<ReadFMemBase, 0>;
-def : ReadAdvance<ReadFAdd16, 0>;
-def : ReadAdvance<ReadFAdd32, 0>;
-def : ReadAdvance<ReadFAdd64, 0>;
-def : ReadAdvance<ReadFMul16, 0>;
-def : ReadAdvance<ReadFMA16, 0>;
-def : ReadAdvance<ReadFMA16Addend, 0>;
-def : ReadAdvance<ReadFMul32, 0>;
-def : ReadAdvance<ReadFMul64, 0>;
-def : ReadAdvance<ReadFMA32, 0>;
-def : ReadAdvance<ReadFMA32Addend, 0>;
-def : ReadAdvance<ReadFMA64, 0>;
-def : ReadAdvance<ReadFMA64Addend, 0>;
-def : ReadAdvance<ReadFDiv16, 0>;
-def : ReadAdvance<ReadFDiv32, 0>;
-def : ReadAdvance<ReadFDiv64, 0>;
-def : ReadAdvance<ReadFSqrt16, 0>;
-def : ReadAdvance<ReadFSqrt32, 0>;
-def : ReadAdvance<ReadFSqrt64, 0>;
-def : ReadAdvance<ReadFCmp16, 0>;
-def : ReadAdvance<ReadFCmp32, 0>;
-def : ReadAdvance<ReadFCmp64, 0>;
-def : ReadAdvance<ReadFSGNJ16, 0>;
-def : ReadAdvance<ReadFSGNJ32, 0>;
-def : ReadAdvance<ReadFSGNJ64, 0>;
-def : ReadAdvance<ReadFMinMax16, 0>;
-def : ReadAdvance<ReadFMinMax32, 0>;
-def : ReadAdvance<ReadFMinMax64, 0>;
-def : ReadAdvance<ReadFCvtF16ToI32, 0>;
-def : ReadAdvance<ReadFCvtF16ToI64, 0>;
-def : ReadAdvance<ReadFCvtF32ToI32, 0>;
-def : ReadAdvance<ReadFCvtF32ToI64, 0>;
-def : ReadAdvance<ReadFCvtF64ToI32, 0>;
-def : ReadAdvance<ReadFCvtF64ToI64, 0>;
-def : ReadAdvance<ReadFCvtI32ToF16, 0>;
-def : ReadAdvance<ReadFCvtI32ToF32, 0>;
-def : ReadAdvance<ReadFCvtI32ToF64, 0>;
-def : ReadAdvance<ReadFCvtI64ToF16, 0>;
-def : ReadAdvance<ReadFCvtI64ToF32, 0>;
-def : ReadAdvance<ReadFCvtI64ToF64, 0>;
-def : ReadAdvance<ReadFCvtF32ToF64, 0>;
-def : ReadAdvance<ReadFCvtF64ToF32, 0>;
-def : ReadAdvance<ReadFCvtF16ToF32, 0>;
-def : ReadAdvance<ReadFCvtF32ToF16, 0>;
-def : ReadAdvance<ReadFCvtF16ToF64, 0>;
-def : ReadAdvance<ReadFCvtF64ToF16, 0>;
-def : ReadAdvance<ReadFMovF16ToI16, 0>;
-def : ReadAdvance<ReadFMovI16ToF16, 0>;
-def : ReadAdvance<ReadFMovF32ToI32, 0>;
-def : ReadAdvance<ReadFMovI32ToF32, 0>;
-def : ReadAdvance<ReadFMovF64ToI64, 0>;
-def : ReadAdvance<ReadFMovI64ToF64, 0>;
-def : ReadAdvance<ReadFClass16, 0>;
-def : ReadAdvance<ReadFClass32, 0>;
-def : ReadAdvance<ReadFClass64, 0>;
-
-// Bitmanip
-def : ReadAdvance<ReadRotateImm, 0>;
-def : ReadAdvance<ReadRotateImm32, 0>;
-def : ReadAdvance<ReadRotateReg, 0>;
-def : ReadAdvance<ReadRotateReg32, 0>;
-def : ReadAdvance<ReadCLZ, 0>;
-def : ReadAdvance<ReadCLZ32, 0>;
-def : ReadAdvance<ReadCTZ, 0>;
-def : ReadAdvance<ReadCTZ32, 0>;
-def : ReadAdvance<ReadCPOP, 0>;
-def : ReadAdvance<ReadCPOP32, 0>;
-def : ReadAdvance<ReadORCB, 0>;
-def : ReadAdvance<ReadIMinMax, 0>;
-def : ReadAdvance<ReadREV8, 0>;
-def : ReadAdvance<ReadSHXADD, 0>;
-def : ReadAdvance<ReadSHXADD32, 0>;
-// Single-bit instructions
-def : ReadAdvance<ReadSingleBit, 0>;
-def : ReadAdvance<ReadSingleBitImm, 0>;
+ let Latency = 12, ReleaseAtCycles = [12] in {
+ def : WriteRes<WriteFDiv64, [AscalonFP]>;
+ def : WriteRes<WriteFSqrt64, [AscalonFP]>;
+ }
-//===----------------------------------------------------------------------===//
-// Vector
-def : WriteRes<WriteRdVLENB, [AscalonFXA]>;
-
-// Configuration-Setting Instructions
-def : WriteRes<WriteVSETVLI, [AscalonV]>;
-def : WriteRes<WriteVSETIVLI, [AscalonV]>;
-let Latency = 2 in {
- def : WriteRes<WriteVSETVL, [AscalonV]>;
-}
+ // Conversions
+ def : WriteRes<WriteFCvtI32ToF16, [AscalonFXB]>;
+ def : WriteRes<WriteFCvtI32ToF32, [AscalonFXB]>;
+ def : WriteRes<WriteFCvtI32ToF64, [AscalonFXB]>;
+ def : WriteRes<WriteFCvtI64ToF16, [AscalonFXB]>;
+ def : WriteRes<WriteFCvtI64ToF32, [AscalonFXB]>;
+ def : WriteRes<WriteFCvtI64ToF64, [AscalonFXB]>;
+ def : WriteRes<WriteFCvtF16ToI32, [AscalonFXA]>;
+ def : WriteRes<WriteFCvtF16ToI64, [AscalonFXA]>;
+ def : WriteRes<WriteFCvtF16ToF32, [AscalonFP]>;
+ def : WriteRes<WriteFCvtF16ToF64, [AscalonFP]>;
+ def : WriteRes<WriteFCvtF32ToI32, [AscalonFXA]>;
+ def : WriteRes<WriteFCvtF32ToI64, [AscalonFXA]>;
+ def : WriteRes<WriteFCvtF32ToF16, [AscalonFP]>;
+ def : WriteRes<WriteFCvtF32ToF64, [AscalonFP]>;
+ def : WriteRes<WriteFCvtF64ToI32, [AscalonFXA]>;
+ def : WriteRes<WriteFCvtF64ToI64, [AscalonFXA]>;
+ def : WriteRes<WriteFCvtF64ToF16, [AscalonFP]>;
+ def : WriteRes<WriteFCvtF64ToF32, [AscalonFP]>;
+
+ def : WriteRes<WriteFClass16, [AscalonFP]>;
+ def : WriteRes<WriteFClass32, [AscalonFP]>;
+ def : WriteRes<WriteFClass64, [AscalonFP]>;
+ def : WriteRes<WriteFCmp16, [AscalonFP]>;
+ def : WriteRes<WriteFCmp32, [AscalonFP]>;
+ def : WriteRes<WriteFCmp64, [AscalonFP]>;
+
+ def : WriteRes<WriteFMovI16ToF16, [AscalonFXB]>;
+ def : WriteRes<WriteFMovF16ToI16, [AscalonFXA]>;
+ def : WriteRes<WriteFMovI32ToF32, [AscalonFXB]>;
+ def : WriteRes<WriteFMovF32ToI32, [AscalonFXA]>;
+ def : WriteRes<WriteFMovI64ToF64, [AscalonFXB]>;
+ def : WriteRes<WriteFMovF64ToI64, [AscalonFXA]>;
+
+ // Others
+ def : WriteRes<WriteCSR, [AscalonFXA]>;
+ def : WriteRes<WriteNop, [AscalonFX]>;
+
+ def : InstRW<[WriteIALU], (instrs COPY)>;
+
+
//===--------------------------------------------------------------------===//
+ // Bypass and advance
+ def : ReadAdvance<ReadJmp, 0>;
+ def : ReadAdvance<ReadJalr, 0>;
+ def : ReadAdvance<ReadCSR, 0>;
+ def : ReadAdvance<ReadStoreData, 0>;
+ def : ReadAdvance<ReadMemBase, 0>;
+ def : ReadAdvance<ReadIALU, 0>;
+ def : ReadAdvance<ReadIALU32, 0>;
+ def : ReadAdvance<ReadShiftImm, 0>;
+ def : ReadAdvance<ReadShiftImm32, 0>;
+ def : ReadAdvance<ReadShiftReg, 0>;
+ def : ReadAdvance<ReadShiftReg32, 0>;
+ def : ReadAdvance<ReadIDiv, 0>;
+ def : ReadAdvance<ReadIDiv32, 0>;
+ def : ReadAdvance<ReadIRem, 0>;
+ def : ReadAdvance<ReadIRem32, 0>;
+ def : ReadAdvance<ReadIMul, 0>;
+ def : ReadAdvance<ReadIMul32, 0>;
+ def : ReadAdvance<ReadAtomicWA, 0>;
+ def : ReadAdvance<ReadAtomicWD, 0>;
+ def : ReadAdvance<ReadAtomicDA, 0>;
+ def : ReadAdvance<ReadAtomicDD, 0>;
+ def : ReadAdvance<ReadAtomicLDW, 0>;
+ def : ReadAdvance<ReadAtomicLDD, 0>;
+ def : ReadAdvance<ReadAtomicSTW, 0>;
+ def : ReadAdvance<ReadAtomicSTD, 0>;
+ def : ReadAdvance<ReadFStoreData, 0>;
+ def : ReadAdvance<ReadFMemBase, 0>;
+ def : ReadAdvance<ReadFAdd16, 0>;
+ def : ReadAdvance<ReadFAdd32, 0>;
+ def : ReadAdvance<ReadFAdd64, 0>;
+ def : ReadAdvance<ReadFMul16, 0>;
+ def : ReadAdvance<ReadFMA16, 0>;
+ def : ReadAdvance<ReadFMA16Addend, 0>;
+ def : ReadAdvance<ReadFMul32, 0>;
+ def : ReadAdvance<ReadFMul64, 0>;
+ def : ReadAdvance<ReadFMA32, 0>;
+ def : ReadAdvance<ReadFMA32Addend, 0>;
+ def : ReadAdvance<ReadFMA64, 0>;
+ def : ReadAdvance<ReadFMA64Addend, 0>;
+ def : ReadAdvance<ReadFDiv16, 0>;
+ def : ReadAdvance<ReadFDiv32, 0>;
+ def : ReadAdvance<ReadFDiv64, 0>;
+ def : ReadAdvance<ReadFSqrt16, 0>;
+ def : ReadAdvance<ReadFSqrt32, 0>;
+ def : ReadAdvance<ReadFSqrt64, 0>;
+ def : ReadAdvance<ReadFCmp16, 0>;
+ def : ReadAdvance<ReadFCmp32, 0>;
+ def : ReadAdvance<ReadFCmp64, 0>;
+ def : ReadAdvance<ReadFSGNJ16, 0>;
+ def : ReadAdvance<ReadFSGNJ32, 0>;
+ def : ReadAdvance<ReadFSGNJ64, 0>;
+ def : ReadAdvance<ReadFMinMax16, 0>;
+ def : ReadAdvance<ReadFMinMax32, 0>;
+ def : ReadAdvance<ReadFMinMax64, 0>;
+ def : ReadAdvance<ReadFCvtF16ToI32, 0>;
+ def : ReadAdvance<ReadFCvtF16ToI64, 0>;
+ def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+ def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+ def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+ def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+ def : ReadAdvance<ReadFCvtI32ToF16, 0>;
+ def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+ def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+ def : ReadAdvance<ReadFCvtI64ToF16, 0>;
+ def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+ def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+ def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+ def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+ def : ReadAdvance<ReadFCvtF16ToF32, 0>;
+ def : ReadAdvance<ReadFCvtF32ToF16, 0>;
+ def : ReadAdvance<ReadFCvtF16ToF64, 0>;
+ def : ReadAdvance<ReadFCvtF64ToF16, 0>;
+ def : ReadAdvance<ReadFMovF16ToI16, 0>;
+ def : ReadAdvance<ReadFMovI16ToF16, 0>;
+ def : ReadAdvance<ReadFMovF32ToI32, 0>;
+ def : ReadAdvance<ReadFMovI32ToF32, 0>;
+ def : ReadAdvance<ReadFMovF64ToI64, 0>;
+ def : ReadAdvance<ReadFMovI64ToF64, 0>;
+ def : ReadAdvance<ReadFClass16, 0>;
+ def : ReadAdvance<ReadFClass32, 0>;
+ def : ReadAdvance<ReadFClass64, 0>;
+
+ // Bitmanip
+ def : ReadAdvance<ReadRotateImm, 0>;
+ def : ReadAdvance<ReadRotateImm32, 0>;
+ def : ReadAdvance<ReadRotateReg, 0>;
+ def : ReadAdvance<ReadRotateReg32, 0>;
+ def : ReadAdvance<ReadCLZ, 0>;
+ def : ReadAdvance<ReadCLZ32, 0>;
+ def : ReadAdvance<ReadCTZ, 0>;
+ def : ReadAdvance<ReadCTZ32, 0>;
+ def : ReadAdvance<ReadCPOP, 0>;
+ def : ReadAdvance<ReadCPOP32, 0>;
+ def : ReadAdvance<ReadORCB, 0>;
+ def : ReadAdvance<ReadIMinMax, 0>;
+ def : ReadAdvance<ReadREV8, 0>;
+ def : ReadAdvance<ReadSHXADD, 0>;
+ def : ReadAdvance<ReadSHXADD32, 0>;
+ // Single-bit instructions
+ def : ReadAdvance<ReadSingleBit, 0>;
+ def : ReadAdvance<ReadSingleBitImm, 0>;
+
+
//===--------------------------------------------------------------------===//
+ // Vector
+ def : WriteRes<WriteRdVLENB, [AscalonFXA]>;
-// Vector Loads and Stores
-foreach mx = SchedMxList in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles in {
- defm "" : LMULWriteResMX<"WriteVLDE", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDFF", [AscalonLS], mx, IsWorstCase>;
+ // Configuration-Setting Instructions
+ def : WriteRes<WriteVSETVLI, [AscalonV]>;
+ def : WriteRes<WriteVSETIVLI, [AscalonV]>;
+ let Latency = 2 in {
+ def : WriteRes<WriteVSETVL, [AscalonV]>;
}
- defm "" : LMULWriteResMX<"WriteVSTE", [AscalonLS], mx, IsWorstCase>;
-}
-foreach mx = SchedMxList in {
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- defm "" : LMULWriteResMX<"WriteVLDM", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
-}
+ // Vector Loads and Stores
+ foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [AscalonLS], mx, IsWorstCase>;
+ }
+ defm "" : LMULWriteResMX<"WriteVSTE", [AscalonLS], mx, IsWorstCase>;
+ }
-foreach mx = SchedMxListEEW8 in {
- defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles in {
- defm "" : LMULWriteResMX<"WriteVLDS8", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX8", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX8", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS8", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX8", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
+ foreach mx = SchedMxList in {
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ defm "" : LMULWriteResMX<"WriteVLDM", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
}
-}
-foreach mx = SchedMxListEEW16 in {
- defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles in {
- defm "" : LMULWriteResMX<"WriteVLDS16", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX16", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX16", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS16", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX16", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
+
+ foreach mx = SchedMxListEEW8 in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDS8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
+ }
}
-}
-foreach mx = SchedMxListEEW32 in {
- defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles in {
- defm "" : LMULWriteResMX<"WriteVLDS32", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX32", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX32", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS32", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX32", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
+ foreach mx = SchedMxListEEW16 in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDS16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
+ }
}
-}
-foreach mx = SchedMxListEEW64 in {
- defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles in {
- defm "" : LMULWriteResMX<"WriteVLDS64", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDUX64", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLDOX64", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTS64", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTUX64", [AscalonLS], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSTOX64", [AscalonLS], mx, IsWorstCase>;
+ foreach mx = SchedMxListEEW32 in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDS32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
+ }
+ }
+ foreach mx = SchedMxListEEW64 in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLDS64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTS64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX64", [AscalonLS], mx, IsWorstCase>;
+ }
}
-}
-// VLD*R is not LMUL aware
-def : WriteRes<WriteVLD1R, [AscalonLS]>;
-def : WriteRes<WriteVLD2R, [AscalonLS]>;
-def : WriteRes<WriteVLD4R, [AscalonLS]>;
-def : WriteRes<WriteVLD8R, [AscalonLS]>;
-// VST*R is not LMUL aware
-def : WriteRes<WriteVST1R, [AscalonLS]>;
-def : WriteRes<WriteVST2R, [AscalonLS]>;
-def : WriteRes<WriteVST4R, [AscalonLS]>;
-def : WriteRes<WriteVST8R, [AscalonLS]>;
-
-// Segmented Loads and Stores
-foreach mx = SchedMxList in {
- foreach eew = [8, 16, 32, 64] in {
- foreach nf=2-8 in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles in {
- defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
+ // VLD*R is not LMUL aware
+ def : WriteRes<WriteVLD1R, [AscalonLS]>;
+ def : WriteRes<WriteVLD2R, [AscalonLS]>;
+ def : WriteRes<WriteVLD4R, [AscalonLS]>;
+ def : WriteRes<WriteVLD8R, [AscalonLS]>;
+ // VST*R is not LMUL aware
+ def : WriteRes<WriteVST1R, [AscalonLS]>;
+ def : WriteRes<WriteVST2R, [AscalonLS]>;
+ def : WriteRes<WriteVST4R, [AscalonLS]>;
+ def : WriteRes<WriteVST8R, [AscalonLS]>;
+
+ // Segmented Loads and Stores
+ foreach mx = SchedMxList in {
+ foreach eew = [8, 16, 32, 64] in {
+ foreach nf=2-8 in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1,
Cycles)] in
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
}
- let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1,
Cycles)] in
- defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
}
}
-}
-foreach mx = SchedMxList in {
- foreach nf=2-8 in {
- foreach eew = [8, 16, 32, 64] in {
- defvar Cycles = AscalonGetCyclesStridedSegmented<mx, eew>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles in {
- defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [AscalonLS],
mx, IsWorstCase>;
+ foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar Cycles = AscalonGetCyclesStridedSegmented<mx, eew>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles in {
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew,
[AscalonLS], mx, IsWorstCase>;
+ }
}
}
}
-}
-// Vector Fixed-Point Arithmetic Instructions
-foreach mx = SchedMxList in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULWriteResMX<"WriteVSALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVAALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVAALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSMulV", [AscalonFXA, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSMulX", [AscalonFXA, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSShiftV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSShiftX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSShiftI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ // Vector Fixed-Point Arithmetic Instructions
+ foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVSALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulV", [AscalonFXA, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [AscalonFXA, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ }
}
-}
-// Narrowing
-foreach mx = SchedMxListW in {
- defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULWriteResMX<"WriteVNClipV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVNClipX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVNClipI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ // Narrowing
+ foreach mx = SchedMxListW in {
+ defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVNClipV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ }
}
-}
-// Configuration-Setting Instructions
-def : ReadAdvance<ReadVSETVLI, 1>;
-def : ReadAdvance<ReadVSETVL, 1>;
-
-// Vector Loads and Stores
-def : ReadAdvance<ReadVLDX, 0>;
-def : ReadAdvance<ReadVSTX, 0>;
-defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
-defm "" : LMULReadAdvance<"ReadVSTM", 0>;
-def : ReadAdvance<ReadVLDSX, 0>;
-def : ReadAdvance<ReadVSTSX, 0>;
-defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
-defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
-defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
-defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
-// LMUL Aware
-def : ReadAdvance<ReadVST1R, 0>;
-def : ReadAdvance<ReadVST2R, 0>;
-def : ReadAdvance<ReadVST4R, 0>;
-def : ReadAdvance<ReadVST8R, 0>;
-
-// Vector Integer Arithmetic Instructions
-foreach mx = SchedMxList in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULWriteResMX<"WriteVIALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUMV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUMX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICALUMI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVShiftV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVShiftX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVShiftI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMinMaxV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMinMaxX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMulV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMulX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMulAddV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMulAddX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMergeV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMergeX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMergeI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMovV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMovX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIMovI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVICmpI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- }
-}
-foreach mx = SchedMxList in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULWriteResMX<"WriteVExtV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- }
-}
-foreach mx = SchedMxList in {
- foreach sew = SchedSEWSet<mx>.val in {
- defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ // Configuration-Setting Instructions
+ def : ReadAdvance<ReadVSETVLI, 1>;
+ def : ReadAdvance<ReadVSETVL, 1>;
+
+ // Vector Loads and Stores
+ def : ReadAdvance<ReadVLDX, 0>;
+ def : ReadAdvance<ReadVSTX, 0>;
+ defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+ def : ReadAdvance<ReadVLDSX, 0>;
+ def : ReadAdvance<ReadVSTSX, 0>;
+ defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+ defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+ defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+ defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+ // LMUL Aware
+ def : ReadAdvance<ReadVST1R, 0>;
+ def : ReadAdvance<ReadVST2R, 0>;
+ def : ReadAdvance<ReadVST4R, 0>;
+ def : ReadAdvance<ReadVST8R, 0>;
+
+ // Vector Integer Arithmetic Instructions
+ foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [AscalonFX, AscalonV], mx,
sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [AscalonFX, AscalonV], mx,
sew, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
}
}
-}
-
-// Widening
-foreach mx = SchedMxListW in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULWriteResMX<"WriteVIWALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIWALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIWALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIWMulV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIWMulX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIWMulAddV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVIWMulAddX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVExtV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ }
}
-}
-// Narrowing
-foreach mx = SchedMxListW in {
- defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULWriteResMX<"WriteVNShiftV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVNShiftX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVNShiftI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
+ }
+ }
}
-}
-// Vector Floating-Point Instructions
-foreach mx = SchedMxListF in {
- foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ // Widening
+ foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF,
isF=1>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
}
}
-}
-foreach mx = SchedMxList in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [AscalonFPA, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFClassV", [AscalonFP, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFMergeV", [AscalonFP, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFMovV", [AscalonFP, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFCmpV", [AscalonFP, AscalonV], mx,
IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFCmpF", [AscalonFP, AscalonV], mx,
IsWorstCase>;
- }
-}
-foreach mx = SchedMxListF in {
- foreach sew = SchedSEWSet<mx, isF=1>.val in {
- defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ // Narrowing
+ foreach mx = SchedMxListW in {
+ defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
- defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [AscalonFP, AscalonV],
mx, sew, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [AscalonFX, AscalonV], mx,
IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [AscalonFX, AscalonV], mx,
IsWorstCase>;
}
}
-}
-// Widening
-foreach mx = SchedMxListW in {
- foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
- defvar Cycles = AscalonGetCyclesDefault<mx>.c;
- defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in
- defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [AscalonFXB, AscalonV],
mx, sew, IsWorstCase>;
+ // Vector Floating-Point Instructions
+ foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF,
isF=1>.c;
+ // FP64 add/mul/fma have reduced throughput on Ascalon XG.
+ defvar IsFP64 = !and(ReducedFP64Vec, !eq(sew, 64));
+ defvar FP64 = AscalonXGFP64Vec<Cycles>;
+ defvar FPVRes = !if(IsFP64, [AscalonFP, AscalonV, AscalonFP64V],
+ [AscalonFP, AscalonV]);
+ let Latency = !if(IsFP64, FP64.Latency, Cycles),
+ ReleaseAtCycles = !if(IsFP64, [1, Cycles, FP64.ReleaseAtCycles],
+ [1, Cycles]) in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", FPVRes, mx, sew,
IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", FPVRes, mx, sew,
IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", FPVRes, mx, sew,
IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", FPVRes, mx, sew,
IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", FPVRes, mx, sew,
IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", FPVRes, mx, sew,
IsWorstCase>;
+ }
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [AscalonFP,
AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [AscalonFP,
AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [AscalonFP,
AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [AscalonFP,
AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [AscalonFP,
AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [AscalonFP,
AscalonV], mx, sew, IsWorstCase>;
----------------
mshockwave wrote:
is there any reason these instructions are not subject to reduced FP64
throughput?
https://github.com/llvm/llvm-project/pull/229030
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